丝印：V00；Package：SOT-753；Single 2-input NAND gate

DESCRIPTION The 74LVC1G00 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment. Schm

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PHI

飞利浦

丝印：V00；Package：SOT-753；Single 2-input NAND gate

description The 74LVC1G00 provides the single 2-input NAND function. Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment. Schmitt trigger action at all inputs makes the circuit tolerant for slower inpu

文件：87.47 Kbytes 页数：14 Pages

恩XP

丝印：V00；Package：SOT753；Single 2-input NAND gate

1. General description The 74LVC1G00 is a single 2-input NAND gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower i

文件：256.38 Kbytes 页数：16 Pages

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

丝印：V00；Package：SC-74A；Single 2-input NAND gate

1. General description The 74LVC1G00-Q100 is a single 2-input NAND gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slo

文件：232 Kbytes 页数：12 Pages

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

丝印：V00；Package：XSON5；Single 2-input NAND gate

1. General description The 74LVC1G00-Q100 is a single 2-input NAND gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slo

文件：232 Kbytes 页数：12 Pages

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

丝印：V00；Package：SOT765-1；Dual 2-input NAND gate

1. General description The 74LVC2G00 is a dual 2-input NAND gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower in

文件：302.44 Kbytes 页数：20 Pages

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

丝印：V00；Package：SOT902-2；Dual 2-input NAND gate

1. General description The 74LVC2G00 is a dual 2-input NAND gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower in

文件：302.44 Kbytes 页数：20 Pages

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

丝印：V00；Package：SOT833-1；Dual 2-input NAND gate

1. General description The 74LVC2G00 is a dual 2-input NAND gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower in

文件：302.44 Kbytes 页数：20 Pages

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

丝印：V00；Package：SOT-753；Single 2-input NAND gate

文件：425.78 Kbytes 页数：17 Pages

恩XP

丝印：V00；Package：SOT-753；Single 2-input NAND gate

文件：123.76 Kbytes 页数：17 Pages

PHI

飞利浦