2输入与非门

HGSEMI

华冠

丝印：VA；Package：SOT-891；Single 2-input NAND gate

description The 74LVC1G00 provides the single 2-input NAND function. Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment. Schmitt trigger action at all inputs makes the circuit tolerant for slower inpu

文件：87.47 Kbytes 页数：14 Pages

恩XP

丝印：VA；Package：SOT-886；Single 2-input NAND gate

DESCRIPTION The 74LVC1G00 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment. Schm

文件：86.38 Kbytes 页数：15 Pages

PHI

PHI

丝印：VA；Package：SOT-886；Single 2-input NAND gate

description The 74LVC1G00 provides the single 2-input NAND function. Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment. Schmitt trigger action at all inputs makes the circuit tolerant for slower inpu

文件：87.47 Kbytes 页数：14 Pages

恩XP

丝印：VA；Package：SOT886；Single 2-input NAND gate

1. General description The 74LVC1G00 is a single 2-input NAND gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower i

文件：256.38 Kbytes 页数：16 Pages

NEXPERIA

安世

丝印：VA；Package：SOT1115；Single 2-input NAND gate

1. General description The 74LVC1G00 is a single 2-input NAND gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower i

文件：256.38 Kbytes 页数：16 Pages

NEXPERIA

安世

丝印：VA；Package：SOT1202；Single 2-input NAND gate

1. General description The 74LVC1G00 is a single 2-input NAND gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower i

文件：256.38 Kbytes 页数：16 Pages

NEXPERIA

安世

丝印：V00；Package：SOT-753；Single 2-input NAND gate

DESCRIPTION The 74LVC1G00 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment. Schm

文件：86.38 Kbytes 页数：15 Pages

PHI

PHI

丝印：V00；Package：SOT-753；Single 2-input NAND gate

description The 74LVC1G00 provides the single 2-input NAND function. Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment. Schmitt trigger action at all inputs makes the circuit tolerant for slower inpu

文件：87.47 Kbytes 页数：14 Pages

恩XP

丝印：V00；Package：SOT753；Single 2-input NAND gate

1. General description The 74LVC1G00 is a single 2-input NAND gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower i

文件：256.38 Kbytes 页数：16 Pages

NEXPERIA

安世