3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH

文件：106.51 Kbytes 页数：6 Pages

IDT

3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH

文件：106.51 Kbytes 页数：6 Pages

IDT

3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH

文件：106.51 Kbytes 页数：6 Pages

IDT

16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

文件：252.64 Kbytes 页数：15 Pages

NEXPERIA

安世

16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

文件：487.64 Kbytes 页数：12 Pages

TI

德州仪器

16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

The 74LVC16373A and 74LVCH16373A are 16-bit D-type transparent latches featuring separate D-type inputs with bus hold (74LVCH16373A only) for each latch and 3-state outputs for bus-oriented applications. One Latch Enable (LE) input and one Output Enable (OE) are provided for each octal. Inputs can • 5 V tolerant inputs/outputs for interfacing with 5 V logic\n• Wide supply voltage range from 1.2 V to 3.6 V\n• CMOS low power consumption\n• Multibyte flow-through standard pinout architecture\n• Multiple low inductance supply pins for minimum noise and ground bounce\n• Direct interface with TTL l;

Nexperia

安世

16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

The 74LVC16373A-Q100 and 74LVCH16373A-Q100 are 16-bit D-type transparent latches featuring separate D-type inputs with bus hold (74LVCH16373A-Q100 only) for each latch and 3-state outputs for bus-oriented applications. One Latch Enable (LE) input and one Output Enable (OE) are provided for each oc • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n• 5 V tolerant inputs/outputs for interfacing with 5 V logic\n• Wide supply voltage range from 1.2 V to 3.6 V\n• CMOS low power consumption\n• Multibyte flow-throug;

Nexperia

安世

16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

The 74LVC16373A and 74LVCH16373A are 16-bit D-type transparent latches featuring separate D-type inputs with bus hold (74LVCH16373A only) for each latch and 3-state outputs for bus-oriented applications. One Latch Enable (LE) input and one Output Enable (OE) are provided for each octal. Inputs can • 5 V tolerant inputs/outputs for interfacing with 5 V logic\n• CMOS low power consumption\n• Multiple low inductance supply pins for minimum noise and ground bounce\n• All data inputs have bus hold (74LVCH16373A only)\n• Complies with JEDEC standard:• JESD8-7A (1.65 V to 1.95 V)\n• JESD8-C/JESD36 (;

Nexperia

安世

Package：48-TFSOP（0.240"，6.10mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 类别：集成电路（IC） 锁存器 描述：IC TRANS D-TYP LATCH 3ST 48TSSOP

Nexperia USA Inc.

Package：48-TFSOP（0.240"，6.10mm 宽）；包装：管件 类别：集成电路（IC） 锁存器 描述：IC TRANSPARENT LATCH 16B 48TSSOP

Nexperia USA Inc.