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74LVC16373ADGG-Q100中文资料16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state数据手册Nexperia规格书

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厂商型号

74LVC16373ADGG-Q100

功能描述

16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

制造商

Nexperia Nexperia B.V. All rights reserved

中文名称

安世 安世半导体(中国)有限公司

数据手册

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更新时间

2025-9-28 22:59:00

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74LVC16373ADGG-Q100规格书详情

描述 Description

The 74LVC16373A-Q100 and 74LVCH16373A-Q100 are 16-bit D-type transparent latches featuring separate D-type inputs with bus hold (74LVCH16373A-Q100 only) for each latch and 3-state outputs for bus-oriented applications. One Latch Enable (LE) input and one Output Enable (OE) are provided for each octal. Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices in mixed 3.3 V and 5 V applications.
The device consists of two sections of eight D-type transparent latches with 3-state true outputs. When LE is HIGH, data at the Dn inputs enter the latches. In this condition, the latches are transparent, that is, the latch outputs change each time its corresponding D-input changes. The latches store the information that was present at the D-inputs one set-up time (tsu) preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the eight latches are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latches. Bus hold on the data inputs eliminates the need for external pull-up resistors to hold unused inputs.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

特性 Features

• Automotive product qualification in accordance with AEC-Q100 (Grade 1)
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C

• 5 V tolerant inputs/outputs for interfacing with 5 V logic
• Wide supply voltage range from 1.2 V to 3.6 V
• CMOS low power consumption
• Multibyte flow-through standard pinout architecture
• Multiple low inductance supply pins for minimum noise and ground bounce
• Direct interface with TTL levels
• All data inputs have bus hold (74LVCH16373A-Q100 only)
• High-impedance when VCC = 0 V
• Complies with JEDEC standard:
• JESD8-7A (1.65 V to 1.95 V)
• JESD8-5A (2.3 V to 2.7 V)
• JESD8-C/JESD36 (2.7 V to 3.6 V)

• ESD protection:
• MIL-STD-883, method 3015 exceeds 2000 V
• HBM JESD22-A114F exceeds 2000 V
• MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
• CDM ANSI/ESDA/Jedec JS-002 exceeds 1000 V

技术参数

  • 制造商编号

    :74LVC16373ADGG-Q100

  • 生产厂家

    :Nexperia

  • VCC (V)

    :1.2 - 3.6

  • Logic switching levels

    :TTL

  • Output drive capability (mA)

    :± 24

  • tpd (ns)

    :3

  • Power dissipation considerations

    :low

  • Tamb (°C)

    :-40~125

  • Rth(j-a) (K/W)

    :82

  • Ψth(j-top) (K/W)

    :2.0

  • Rth(j-c) (K/W)

    :37

  • Package name

    :TSSOP48

供应商 型号 品牌 批号 封装 库存 备注 价格
恩XP
24+
7350
现货供应,当天可交货!免费送样,原厂技术支持!!!
询价
恩XP
24+
2886
原装现货,免费供样,技术支持,原厂对接
询价
TI/TEXAS
23+
TSSOP
8931
询价
TI(德州仪器)
2511
5904
电子元器件采购降本 30%!盈慧通原厂直采,砍掉中间差价
询价
TI
24+
TSSOP
11659
询价
恩XP
2407+
TSSOP
7750
原装现货!实单直说!特价!
询价
TI
2025+
TSSOP-48
16000
原装优势绝对有货
询价
恩XP
23+
TSSOP
5000
原装正品,假一罚十
询价
Nexperia USA Inc.
24+
48-TSSOP
56200
一级代理/放心采购
询价
TI(德州仪器)
23+
TSSOP-48
9990
原装正品,支持实单
询价