74LVC162373ADL数据手册集成电路（IC）的锁存器规格书PDF

描述 Description

16-bit D-type transparent latch - The 74LVC162373A and 74LVCH162373A are 16-bit D-type transparent latches with separate D-type inputs with bus hold (74LVCH162373A only) for each latch and 3-state outputs for bus-oriented applications. One latch enable (pin nLE) input and one output enable (pin nOE) are provided for each octal. Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices in mixed 3.3 V and 5 V applications. The device consists of two sections of eight D-type transparent latches with 3-state true outputs. When pin nLE is HIGH, data at the corresponding data inputs (pins nDn) enter the latches. In this condition, the latches are transparent, that is, the latch output changes each time its corresponding data inputs changes. When pin nLE is LOW, the latches store the information that was present at the data inputs a set-up time preceding the HIGH to LOW transition of pin nLE.When pin nOE is LOW, the contents of the eight latches are available at the outputs. When pin nOE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the nOE input does not affect the state of the latches. The device is designed with 30 Ω series termination resistors in both HIGH and LOW output stages to reduce line noise. Bus hold on data inputs eliminates the need for external pull-up resistors to hold unused inputs.

特性 Features

·5 V tolerant inputs/outputs for interfacing with 5 V logic
·Wide supply voltage range from 1.2 V to 3.6 V
·CMOS low power consumption
·Multibyte flow-through standard pinout architecture
·Multiple low inductance supply pins for minimum noise and ground bounce
·Direct interface with TTL levels
·All data inputs have bushold (74LVCH162373A only)
·High-impedance when VCC = 0 V
·Complies with JEDEC standard:·JESD8-7A (1.65 V to 1.95 V)
·JESD8-5A (2.3 V to 2.7 V)
·JESD8-C/JESD36 (2.7 V to 3.6 V)