16-bit D-type transparent latch with 5 Volt tolerant inputs/outputs 3-State

DESCRIPTION The 74LVC(H)16373A is a 16-bit D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. One Latch Enable (LE) input and one Output Enable (OE) are provided for each octal. Inputs can be driven from either 3.3 or 5 V

文件：83.79 Kbytes 页数：10 Pages

PHI

PHI

16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

DESCRIPTION The 74LVC(H)16373A is a 16-bit D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. One Latch Enable (LE) input and one Output Enable (OE) are provided for each octal. Inputs can be driven from either 3.3 or 5 V

文件：114.24 Kbytes 页数：17 Pages

PHI

PHI

3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O

FEATURES: • Typical tSK(o) (Output Skew) 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • CMOS power levels (0.4μ W typ. static) • All inputs, outputs, and I/O are 5V to

文件：284.25 Kbytes 页数：7 Pages

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瑞萨

3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O

FEATURES: • Typical tSK(o) (Output Skew) 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • CMOS power levels (0.4μ W typ. static) • All inputs, outputs, and I/O are 5V to

文件：284.25 Kbytes 页数：7 Pages

RENESAS

瑞萨

3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O

FEATURES: • Typical tSK(o) (Output Skew) 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • CMOS power levels (0.4μ W typ. static) • All inputs, outputs, and I/O are 5V to

文件：284.25 Kbytes 页数：7 Pages

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瑞萨

3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O

FEATURES: • Typical tSK(o) (Output Skew) 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • CMOS power levels (0.4μ W typ. static) • All inputs, outputs, and I/O are 5V to

文件：284.25 Kbytes 页数：7 Pages

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瑞萨

丝印：LVC16373；Package：TSSOP；16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

FEATURES · Member of the Texas Instruments Widebus™ Family · EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process · Typical VOLP (Output Ground Bounce) 2 V at VCC = 3.3 V, TA = 25°C · Latch-Up Performance

文件：448.91 Kbytes 页数：16 Pages

TI

德州仪器

16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

文件：212.22 Kbytes 页数：17 Pages

PHI

PHI

16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

文件：252.64 Kbytes 页数：15 Pages

NEXPERIA

安世

16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

文件：329.51 Kbytes 页数：15 Pages

TI

德州仪器