3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O

FEATURES: • Typical tSK(o) (Output Skew) 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • CMOS power levels (0.4μ W typ. static) • All inputs, outputs, and I/O are 5V to

文件：262.74 Kbytes 页数：7 Pages

RENESAS

瑞萨

3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O

FEATURES: • Typical tSK(o) (Output Skew) 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • CMOS power levels (0.4μ W typ. static) • All inputs, outputs, and I/O are 5V to

文件：262.74 Kbytes 页数：7 Pages

RENESAS

瑞萨

16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state

General description The 74LVC16374A-Q100 and 74LVCH16374A-Q100 are 16-bit edge-triggered flip-flops featuring separate D-type inputs with bus hold (74LVCH16374A-Q100 only) for each flip-flop and 3-state outputs for bus-oriented applications. It consists of two sections of eight positive edge-trig

文件：230.64 Kbytes 页数：14 Pages

NEXPERIA

安世

Presettable synchronous 4-bit binary counter; synchronous reset

1. General description The 74LVC163 is a synchronous presettable binary counter which features an internal look-ahead carry and can be used for high-speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (pin CP)

文件：295.6 Kbytes 页数：18 Pages

NEXPERIA

安世

Presettable synchronous 4-bit binary counter; synchronous reset

1. General description The 74LVC163 is a synchronous presettable binary counter which features an internal look-ahead carry and can be used for high-speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (pin CP)

文件：295.6 Kbytes 页数：18 Pages

NEXPERIA

安世

Presettable synchronous 4-bit binary counter; synchronous reset

DESCRIPTION The 74LVC163 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. FEATURES • Wide supply voltage range of 1.2 V to 3.6 V • In accordance with JEDEC standard no. 8–1A • Inputs accept voltages up to 5.5 V • C

文件：115.93 Kbytes 页数：12 Pages

PHI

PHI

Presettable synchronous 4-bit binary counter; synchronous reset

DESCRIPTION The 74LVC163 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. FEATURES • Wide supply voltage range of 1.2 V to 3.6 V • In accordance with JEDEC standard no. 8–1A • Inputs accept voltages up to 5.5 V • C

文件：115.93 Kbytes 页数：12 Pages

PHI

PHI

Presettable synchronous 4-bit binary counter; synchronous reset

1. General description The 74LVC163 is a synchronous presettable binary counter which features an internal look-ahead carry and can be used for high-speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (pin CP)

文件：295.6 Kbytes 页数：18 Pages

NEXPERIA

安世

Presettable synchronous 4-bit binary counter; synchronous reset

DESCRIPTION The 74LVC163 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. FEATURES • Wide supply voltage range of 1.2 V to 3.6 V • In accordance with JEDEC standard no. 8–1A • Inputs accept voltages up to 5.5 V • C

文件：115.93 Kbytes 页数：12 Pages

PHI

PHI

Presettable synchronous 4-bit binary counter; synchronous reset

DESCRIPTION The 74LVC163 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. FEATURES • Wide supply voltage range of 1.2 V to 3.6 V • In accordance with JEDEC standard no. 8–1A • Inputs accept voltages up to 5.5 V • C

文件：115.93 Kbytes 页数：12 Pages

PHI

PHI