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74LVC163PW集成电路(IC)计数器除法器规格书PDF中文资料
厂商型号 |
74LVC163PW |
参数属性 | 74LVC163PW 封装/外壳为16-TSSOP(0.173",4.40mm 宽);包装为卷带(TR)剪切带(CT)Digi-Reel® 得捷定制卷带;类别为集成电路(IC) > 计数器,除法器;产品描述:IC 4-BIT SYNC BIN CNTR 16TSSOP |
功能描述 | Presettable synchronous 4-bit binary counter; synchronous reset |
文件大小 |
295.6 Kbytes |
页面数量 |
18 页 |
生产厂商 | Nexperia B.V. All rights reserved |
企业简称 |
NEXPERIA【安世】 |
中文名称 | 安世半导体(中国)有限公司官网 |
原厂标识 | |
数据手册 | |
更新时间 | 2024-6-15 21:06:00 |
74LVC163PW规格书详情
1. General description
The 74LVC163 is a synchronous presettable binary counter which features an internal look-ahead
carry and can be used for high-speed counting. Synchronous operation is provided by having all
flip-flops clocked simultaneously on the positive-going edge of the clock (pin CP). The outputs (pins
Q0 to Q3) of the counters may be preset to a HIGH-level or LOW-level. A LOW-level at the parallel
enable input (pin PE) disables the counting action and causes the data at the data inputs (pins
D0 to D3) to be loaded into the counter on the positive-going edge of the clock (provided that the
set-up and hold time requirements for PE are met). Preset takes place regardless of the levels at
count enable inputs (pin CEP and CET). A LOW-level at the master reset input (pin MR) sets all
four outputs of the flip-flops (pins Q0 to Q3) to LOW-level after the next positive-going transition
on the clock input (pin CP) (provided that the set-up and hold time requirements for PE are met).
This action occurs regardless of the levels at input pins PE, CET and CEP. This synchronous reset
feature enables the designer to modify the maximum count with only one external NAND gate.
The look-ahead carry simplifies serial cascading of the counters. Both count enable inputs (pin
CEP and CET) must be HIGH in count. The CET input is fed forward to enable the terminal count
output (pin TC). The TC output thus enabled will produce a HIGH output pulse of a duration
approximately equal to a HIGH-level output of Q0. This pulse can be used to enable the next
cascaded stage.
The maximum clock frequency for the cascaded counters is determined by tPHL (propagation delay
CP to TC) and tsu (set-up time CEP to CP) according to the formula: .
2. Features and benefits
• Wide supply voltage range from 1.2 V to 3.6 V
• Inputs accept voltages up to 5.5 V
• CMOS low power consumption
• Direct interface with TTL levels
• Synchronous reset
• Synchronous counting and loading
• Two count enable inputs for n-bit cascading
• Positive edge-triggered clock
• Complies with JEDEC standard:
• JESD8-7A (1.65 V to 1.95 V)
• JESD8-5A (2.3 V to 2.7 V)
• JESD8-C/JESD36 (2.7 V to 3.6 V)
• ESD protection:
• HBM JESD22-A114F exceeds 2000 V
• MM JESD22-A115-B exceeds 200 V
• CDM JESD22-C101E exceeds 1000 V
• Specified from -40 °C to +85 °C and -40 °C to 125 °C
74LVC163PW属于集成电路(IC) > 计数器,除法器。安世半导体(中国)有限公司制造生产的74LVC163PW计数器,除法器计数器和除法器 IC 是数字逻辑器件,可对输入发生的逻辑转换进行计数,然后使用多个并行输出重新发送累加的计数,和/或生成单个输出信号转换,从而对应用某些整数数量输入信号转换进行响应。除了简单的事件计数,它们还可用于各种频率合成应用。
产品属性
- 产品编号:
74LVC163PW,118
- 制造商:
Nexperia USA Inc.
- 类别:
集成电路(IC) > 计数器,除法器
- 系列:
74LVC
- 包装:
卷带(TR)剪切带(CT)Digi-Reel® 得捷定制卷带
- 逻辑类型:
二进制计数器
- 方向:
上
- 复位:
同步
- 定时:
同步
- 触发器类型:
正边沿
- 工作温度:
-40°C ~ 125°C
- 安装类型:
表面贴装型
- 封装/外壳:
16-TSSOP(0.173",4.40mm 宽)
- 供应商器件封装:
16-TSSOP
- 描述:
IC 4-BIT SYNC BIN CNTR 16TSSOP
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
NXP |
21+ |
TSSOP |
35400 |
一级代理/放心采购 |
询价 | ||
NXP/恩智浦 |
23+ |
NA/ |
810 |
优势代理渠道,原装正品,可全系列订货开增值税票 |
询价 | ||
NXP |
23+ |
TSSOP |
20000 |
询价 | |||
NXP |
1815+ |
TSSOP16 |
6528 |
只做原装正品现货!或订货,假一赔十! |
询价 | ||
NXP |
2023+ |
TSSOP |
80000 |
一级代理/分销渠道价格优势 十年芯程一路只做原装正品 |
询价 | ||
Nexperia(安世) |
1923+ |
TSSOP-16 |
2260 |
向鸿只做原装正品,我们没有假货!仓库库存优势 |
询价 | ||
PHI |
08+ |
TSSOP |
1535 |
询价 | |||
NXP(恩智浦) |
23+ |
标准封装 |
6000 |
正规渠道,只有原装! |
询价 | ||
PHILIPS |
23+ |
589610 |
新到现货 原厂一手货源 价格秒杀代理! |
询价 | |||
74LVC163PW |
2575 |
2575 |
询价 |