1. General description

The 74LVC16374A; 74LVCH16374A is a 16-bit edge-triggered D-type flip-flop with 3-state outputs.

The device can be used as two 8-bit flip-flops or one 16-bit flip-flop. The device features two clocks

(1CP and 2CP) and two output enables (1OE and 2OE), each controlling 8-bits. The flip-flops

will store the state of their individual D-inputs that meet the set-up and hold time requirements

on the LOW-to-HIGH clock (nCP) transition. A HIGH on nOE causes the outputs to assume a

high-impedance OFF-state. Operation of the nOE input does not affect the state of the flip-flops.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices

as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry

disables the output, preventing the potentially damaging backflow current through the device when

it is powered down.

2. Features and benefits

. Overvoltage tolerant inputs to 5.5 V

. Wide supply voltage range from 1.2 V to 3.6 V

. CMOS low power dissipation

. Multibyte flow-through standard pinout architecture

. Low inductance multiple supply pins for minimum noise and ground bounce

. Direct interface with TTL levels

. All data inputs have bus hold (74LVCH16374A only)

. High-impedance outputs when VCC = 0 V

. IOFF circuitry provides partial Power-down mode operation

. Complies with JEDEC standard:

. JESD8-7A (1.65 V to 1.95 V)

. JESD8-5A (2.3 V to 2.7 V)

. JESD8-C/JESD36 (2.7 V to 3.6 V)

. ESD protection:

. HBM JESD22-A114F exceeds 2000 V

. MM JESD22-A115-B exceeds 200 V

. CDM JESD22-C101E exceeds 1000 V

. Specified from -40 °C to +85 °C and -40 °C to +125 °C

74LVC16374A属于集成电路（IC） > 触发器。安世半导体(中国)有限公司制造生产的74LVC16374A触发器触发器是能够存储单个逻辑状态或信息“位”的基本数字存储器件。这些器件至少有两个输入；一个或多个用于传递要存储的数据，另一个用于指示存储该数据的时间点。不同的触发器类型，例如 D（延迟）、SR（置位复位）和 JK，对提供给其输入的信号有不同的响应，可用于实现不同的逻辑功能。这些器件与锁存器的不同之处在于它们是边缘敏感器件，其保持的逻辑状态仅在接收到有效时钟信号时才会改变。