16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

1. General description The 74LVC16373A and 74LVCH16373A are 16-bit D-type transparent latches with 3-state outputs. The devices can be used as two 8-bit transparent latches or a single 16-bit transparent latch. The devices feature two latch enables (1LE and 2LE) and two output enables (1OE and

文件：261.55 Kbytes 页数：15 Pages

NEXPERIA

安世

丝印：LD373A；Package：TVSOP；SN74LVC16373A 16-Bit Transparent D-Type Latch With 3-State Outputs

1 Features 1• Member of the Texas Instruments Widebus™ Family • Operates From 1.65 V to 3.6 V • Inputs Accept Voltages to 5.5 V • Max tpd of 4.2 ns at 3.3 V • Typical VOLP (Output Ground Bounce) 2 V at VCC = 3.3 V, T

文件：697.75 Kbytes 页数：29 Pages

TI

德州仪器

16-bit D-type transparent latch with 5 Volt tolerant inputs/outputs 3-State

DESCRIPTION The 74LVC(H)16373A is a 16-bit D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. One Latch Enable (LE) input and one Output Enable (OE) are provided for each octal. Inputs can be driven from either 3.3 or 5 V

文件：83.79 Kbytes 页数：10 Pages

PHI

PHI

16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

DESCRIPTION The 74LVC(H)16373A is a 16-bit D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. One Latch Enable (LE) input and one Output Enable (OE) are provided for each octal. Inputs can be driven from either 3.3 or 5 V

文件：114.24 Kbytes 页数：17 Pages

PHI

PHI

3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O

FEATURES: • Typical tSK(o) (Output Skew) 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • CMOS power levels (0.4μ W typ. static) • All inputs, outputs, and I/O are 5V to

文件：284.25 Kbytes 页数：7 Pages

RENESAS

瑞萨

3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O

FEATURES: • Typical tSK(o) (Output Skew) 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • CMOS power levels (0.4μ W typ. static) • All inputs, outputs, and I/O are 5V to

文件：284.25 Kbytes 页数：7 Pages

RENESAS

瑞萨

3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O

FEATURES: • Typical tSK(o) (Output Skew) 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • CMOS power levels (0.4μ W typ. static) • All inputs, outputs, and I/O are 5V to

文件：284.25 Kbytes 页数：7 Pages

RENESAS

瑞萨

3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O

FEATURES: • Typical tSK(o) (Output Skew) 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • CMOS power levels (0.4μ W typ. static) • All inputs, outputs, and I/O are 5V to

文件：284.25 Kbytes 页数：7 Pages

RENESAS

瑞萨

丝印：LVC16373；Package：TSSOP；16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

FEATURES · Member of the Texas Instruments Widebus™ Family · EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process · Typical VOLP (Output Ground Bounce) 2 V at VCC = 3.3 V, TA = 25°C · Latch-Up Performance

文件：448.91 Kbytes 页数：16 Pages

TI

德州仪器

16-bit edge-triggered D-type flip-flop with 5 V tolerant inputs/outputs; 3-state

General description The 74LVC16374A and 74LVCH16374A are 16-bit edge-triggered flip-flops featuring separate D-type inputs with bus hold (74LVCH16374A only) for each flip-flop and 3-state outputs for bus oriented applications. It consists of two sections of eight positive edge-triggered flip-flop

文件：175.05 Kbytes 页数：19 Pages

恩XP