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型号	下载订购	功能描述	制造商上传企业	LOGO
74HCT112	文件：106.77 Kbytes Page：15 Pages	Dual JK flip-flop with set and reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT112 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Asynchronous set and reset • Output capability: standard • ICC category: flip 文件：106.77 Kbytes 页数：15 Pages	PHI 飞利浦	PHI
74HCT112	文件：267.28 Kbytes Page：16 Pages	Dual JK flip-flop with set and reset; negative-edge trigger 1. General description The 74HC112; 74HCT112 is a dual negative-edge triggered JK flip-flop. It features individual J and K inputs, clock (nCP) set (nSD) and reset (nRD) inputs. It also has complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate indepen 文件：267.28 Kbytes 页数：16 Pages	NEXPERIANexperia B.V. All rights reserved 安世安世半导体(中国)有限公司	NEXPERIA
74HCT112D	文件：267.28 Kbytes Page：16 Pages	Dual JK flip-flop with set and reset; negative-edge trigger 1. General description The 74HC112; 74HCT112 is a dual negative-edge triggered JK flip-flop. It features individual J and K inputs, clock (nCP) set (nSD) and reset (nRD) inputs. It also has complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate indepen 文件：267.28 Kbytes 页数：16 Pages	NEXPERIANexperia B.V. All rights reserved 安世安世半导体(中国)有限公司	NEXPERIA
74HCT112D	文件：106.77 Kbytes Page：15 Pages	Dual JK flip-flop with set and reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT112 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Asynchronous set and reset • Output capability: standard • ICC category: flip 文件：106.77 Kbytes 页数：15 Pages	PHI 飞利浦	PHI
74HCT112DB	文件：106.77 Kbytes Page：15 Pages	Dual JK flip-flop with set and reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT112 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Asynchronous set and reset • Output capability: standard • ICC category: flip 文件：106.77 Kbytes 页数：15 Pages	PHI 飞利浦	PHI
74HCT112N	文件：106.77 Kbytes Page：15 Pages	Dual JK flip-flop with set and reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT112 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Asynchronous set and reset • Output capability: standard • ICC category: flip 文件：106.77 Kbytes 页数：15 Pages	PHI 飞利浦	PHI
74HCT112PW	文件：106.77 Kbytes Page：15 Pages	Dual JK flip-flop with set and reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT112 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Asynchronous set and reset • Output capability: standard • ICC category: flip 文件：106.77 Kbytes 页数：15 Pages	PHI 飞利浦	PHI
74HCT112PW	文件：267.28 Kbytes Page：16 Pages	Dual JK flip-flop with set and reset; negative-edge trigger 1. General description The 74HC112; 74HCT112 is a dual negative-edge triggered JK flip-flop. It features individual J and K inputs, clock (nCP) set (nSD) and reset (nRD) inputs. It also has complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate indepen 文件：267.28 Kbytes 页数：16 Pages	NEXPERIANexperia B.V. All rights reserved 安世安世半导体(中国)有限公司	NEXPERIA
74HCT112DB	文件：300 bytes Page：1 Pages	74HCT112DB - dual JK flip-flop with set and reset; negative-edge trigger dual JK flip-flop with set and reset; negative-edge trigger - The 74HC112; 74HCT112 is a dual negative-edge triggered JK flip-flop. It features individual J and K inputs, clock (nCP) set (nSD) and reset (nRD) inputs. It also has complementary nQ and nQ outputs. The set and reset are asynchronous act ·Input levels:·For 74HC112: CMOS level\n·For 74HCT112: TTL level;	Nexperia 安世	Nexperia
74HCT112D-Q100	文件：300 bytes Page：1 Pages	Dual JK flip-flop with set and reset; negative-edge trigger The 74HC112-Q100; 74HCT112-Q100 is a dual negative-edge triggered JK flip-flop. It features individual J and K inputs, clock (nCP) set (nSD) and reset (nRD) inputs. It also has complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the cloc	Nexperia 安世	Nexperia

技术参数

VCC (V)：
4.5 - 5.5
Logic switching levels：
TTL
Output drive capability (mA)：
± 4
tpd (ns)：
19
fmax (MHz)：
70
Power dissipation considerations：
low
Tamb (°C)：
-40~125
Rth(j-a) (K/W)：
75
Ψth(j-top) (K/W)：
1.7
Rth(j-c) (K/W)：
33
Package name：
SO16

供应商	型号	品牌	批号	封装	库存	备注	价格
深圳市一线半导体有限公司	74HCT112		24+		5000	公司存货	询价
深圳市能创芯电子科技有限公司	74HCT112	HARRIS	23+	DP16	3000	原装正品假一罚百!可开增票!	询价
深圳市威尔健半导体有限公司	74HCT112	PHI	23+		50000	全新原装正品现货,支持订货	询价
深圳市恒达亿科技有限公司	74HCT112	HAR	25+	SOP	3200	全新原装、诚信经营、公司现货销售	询价
深圳市瑞卓芯科技有限公司	74HCT112	HARRIS/哈里斯	22+	SOP16	14008	原装正品	询价
上海意淼电子科技有限公司	74HCT112	HAR	23+	NA	20000	全新原装假一赔十	询价
深圳市得捷芯城科技有限公司	74HCT112	PHI	24+	NA/	4313	原装现货,当天可交货,原型号开票	询价
深圳市星佑电子有限公司	74HCT112D	PHI	05+	原厂原装	5001	只做全新原装真实现货供应	询价
深圳市联世界科技有限公司	74HCT112N	PHIL	24+/25+		25	原装正品现货库存价优	询价
深圳市欧立现代科技有限公司	74HCT112N	ph	24+	N/A	6980	原装现货,可开13%税票	询价

更多74HCT112供应商更新时间2025-10-8 16:01:00

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