4-to-16 line decoder/demultiplexer

General description The 74HC154; 74HCT154 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). Features ■ 16-line demultiplexing capability ■ Decodes 4 binary-coded inputs into 16 mutually-exclusive outputs ■ Complies with JEDEC standard no. 7A

文件：138.41 Kbytes 页数：21 Pages

恩XP

4-to-16 line decoder/demultiplexer

1. General description The 74HC154; 74HCT154 is a 4-to-16 line decoder/demultiplexer. It decodes four binary weighted address inputs (A0 to A3) to sixteen mutually exclusive outputs (Y0 to Y15). The device features two input enable (E0 and E1) inputs. A HIGH on either of the input enables force

文件：294.64 Kbytes 页数：17 Pages

NEXPERIA

安世

4-to-16 line decoder/demultiplexer

GENERAL DESCRIPTION The 74HC/HCT154 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • 16-line demultiplexing capability • Decodes 4 binary-coded inputs into one of 16

文件：144.3 Kbytes 页数：22 Pages

PHI

PHI

4-to-16 line decoder/demultiplexer

General description The 74HC154; 74HCT154 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). Features ■ 16-line demultiplexing capability ■ Decodes 4 binary-coded inputs into 16 mutually-exclusive outputs ■ Complies with JEDEC standard no. 7A

文件：138.41 Kbytes 页数：21 Pages

恩XP

Quad 2?묲nput Data Selectors / Multiplexers High?뭁erformance Silicon?묰ate CMOS

The 74HCT157 is identical in pinout to the LS157. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device routes 2 nibbles (A or B) to a single port (Y) as determined by the Select input. The data is presented at the

文件：138.65 Kbytes 页数：9 Pages

ONSEMI

安森美半导体

Quad 2-input multiplexer

GENERAL DESCRIPTION The 74HC/HCT157 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Non-inverting data path • Output capability: standard • ICC category: MSI

文件：44.04 Kbytes 页数：7 Pages

PHI

PHI

Quad 2-input multiplexer

1. General description The 74HC157; 74HCT157 is a quad 2-input multiplexer. The device features select (S) and enable E inputs. A HIGH on S selects data source 1, a LOW data source 0. A HIGH on E forces all the outputs (1Y to 4Y) LOW. Inputs include clamp diodes. This enables the use of current

文件：262.12 Kbytes 页数：15 Pages

NEXPERIA

安世

Quad 2-input multiplexer

1. General description The 74HC157; 74HCT157 is a quad 2-input multiplexer. The device features select (S) and enable E inputs. A HIGH on S selects data source 1, a LOW data source 0. A HIGH on E forces all the outputs (1Y to 4Y) LOW. Inputs include clamp diodes. This enables the use of current

文件：262.12 Kbytes 页数：15 Pages

NEXPERIA

安世

Quad 2-input multiplexer

1. General description The 74HC157-Q100; 74HCT157-Q100 is a quad 2-input multiplexer. The device features select (S) and enable E inputs. A HIGH on S selects data source 1, a LOW data source 0. A HIGH on E forces all the outputs (1Y to 4Y) LOW. Inputs include clamp diodes. This enables the use

文件：261.64 Kbytes 页数：15 Pages

NEXPERIA

安世

Quad 2-input multiplexer

1. General description The 74HC157; 74HCT157 is a quad 2-input multiplexer. The device features select (S) and enable E inputs. A HIGH on S selects data source 1, a LOW data source 0. A HIGH on E forces all the outputs (1Y to 4Y) LOW. Inputs include clamp diodes. This enables the use of current

文件：262.12 Kbytes 页数：15 Pages

NEXPERIA

安世