Triple 3-input AND gate

文件：693.09 Kbytes 页数：13 Pages

NEXPERIA

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Triple 3-input AND gate

文件：693.09 Kbytes 页数：13 Pages

NEXPERIA

安世

Triple 3-input AND gate

文件：693.09 Kbytes 页数：13 Pages

NEXPERIA

安世

J-K Type Flip-Flops

dual JK flip-flop with set and reset; negative-edge trigger - The 74HC112; 74HCT112 is a dual negative-edge triggered JK flip-flop. It features individual J and K inputs, clock (nCP) set (nSD) and reset (nRD) inputs. It also has complementary nQ and nQ outputs. The set and reset are asynchronous act ·Input levels:·For 74HC112: CMOS level\n·For 74HCT112: TTL level;

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Dual JK flip-flop with set and reset; negative-edge trigger

The 74HC112; 74HCT112 is a dual negative-edge triggered JK flip-flop. It features individual J and K inputs, clock (nCP) set (nSD) and reset (nRD) inputs. It also has complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. T • Input levels:• For 74HC112: CMOS level\n• For 74HCT112: TTL level\n\n• Asynchronous set and reset\n• Specified in compliance with JEDEC standard no. 7A\n• ESD protection:• HBM JESD22-A114F exceeds 2000 V\n• MM JESD22-A115-A exceeds 200 V\n\n• Multiple package options\n• Specified from -40 °C to +8;

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Dual JK flip-flop with set and reset; negative-edge trigger

The 74HC112-Q100; 74HCT112-Q100 is a dual negative-edge triggered JK flip-flop. It features individual J and K inputs, clock (nCP) set (nSD) and reset (nRD) inputs. It also has complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the cloc

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安世

Package：16-SOIC（0.154"，3.90mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 功能：设置（预设）和复位 类别：集成电路（IC） 触发器 描述：IC FF JK TYPE DUAL 1BIT 16SO

Nexperia USA Inc.

Package：16-SSOP（0.209"，5.30mm 宽）；包装：卷带（TR） 功能：设置（预设）和复位 类别：集成电路（IC） 触发器 描述：IC FF JK TYPE DUAL 1BIT 16SSOP

Nexperia USA Inc.

Package：16-SSOP（0.209"，5.30mm 宽）；包装：卷带（TR） 功能：设置（预设）和复位 类别：集成电路（IC） 触发器 描述：IC FF JK TYPE DUAL 1BIT 16SSOP

Nexperia USA Inc.