Low-power D-type flip-flop with set and reset; positive-edge trigger

1. General description The 74AUP1G74 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transi

文件：349.69 Kbytes 页数：26 Pages

NEXPERIA

安世

Low-power D-type flip-flop with set and reset; positive-edge trigger

文件：112.63 Kbytes 页数：23 Pages

PHI

PHI

Low-power D-type flip-flop with set and reset; positive-edge trigger

文件：128.09 Kbytes 页数：24 Pages

恩XP

Low Power Single D-Type Positive Edge-Triggered Flip-Flop with Clear and Preset

The 74AUP1G74 is a low power single positive edge-triggered D-Type flip-flop with clear and preset functions. This device can operate in the supply voltage range from 0.8V to 3.6V.\nNo matter what the levels of the other inputs are, the preset (PRE) input or clear (CLR) input can be pulled low to se Wide Supply Voltage Range: 0.8V to 3.6V\nInputs Accept Voltages Higher than the Supply Voltage\n+4mA/-4mA Output Current\nLow Static Power Dissipation: ICC = 1μA (MAX)\nLow Dynamic Power Dissipation: CPD = 5.5pF (TYP) at VCC = 3.3V\nInput Capacitance: CI = 4pF (TYP)\nPropagation Delay: tPD = 9ns (MA;

SGMICRO

圣邦股份

丝印：p74；Package：SOT765-1；Low-power D-type flip-flop with set and reset; positive-edge trigger

1. General description The 74AUP1G74 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transi

文件：349.69 Kbytes 页数：26 Pages

NEXPERIA

安世

丝印：54；Package：SOT1089；Low-power D-type flip-flop with set and reset; positive-edge trigger

1. General description The 74AUP1G74 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transi

文件：349.69 Kbytes 页数：26 Pages

NEXPERIA

安世

丝印：54；Package：SOT1116；Low-power D-type flip-flop with set and reset; positive-edge trigger

1. General description The 74AUP1G74 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transi

文件：349.69 Kbytes 页数：26 Pages

NEXPERIA

安世

丝印：54；Package：SOT1203；Low-power D-type flip-flop with set and reset; positive-edge trigger

1. General description The 74AUP1G74 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transi

文件：349.69 Kbytes 页数：26 Pages

NEXPERIA

安世

丝印：p74；Package：SOT833-1；Low-power D-type flip-flop with set and reset; positive-edge trigger

1. General description The 74AUP1G74 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transi

文件：349.69 Kbytes 页数：26 Pages

NEXPERIA

安世

丝印：54；Package：SOT1233-2；Low-power D-type flip-flop with set and reset; positive-edge trigger

1. General description The 74AUP1G74 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transi

文件：349.69 Kbytes 页数：26 Pages

NEXPERIA

安世