74AUP1G74GX集成电路（IC）的触发器规格书PDF中文资料

厂商型号	74AUP1G74GX
参数属性	74AUP1G74GX 封装/外壳为8-XFDFN 裸露焊盘；包装为卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带；类别为集成电路（IC）的触发器；产品描述：IC FF D-TYPE SNGL 1BIT 8X2SON
功能描述	Low-power D-type flip-flop with set and reset; positive-edge trigger
丝印标识	54
封装外壳	SOT1233-2 / 8-XFDFN 裸露焊盘
文件大小	349.69 Kbytes
页面数量	26 页
生产厂商	NEXPERIA
中文名称	安世
网址	网址
数据手册	下载地址一下载地址二到原厂下载
更新时间	2025-11-17 14:16:00
人工找货	74AUP1G74GX价格和库存，欢迎联系客服免费人工找货

1. General description

The 74AUP1G74 is a single positive edge triggered D-type flip-flop with individual data (D),

clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the

D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will

be stored in the flip-flop and appear at the Q output.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device ensures very low static and dynamic power consumption across the entire VCC range

from 0.8 V to 3.6 V.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry

disables the output, preventing the potentially damaging backflow current through the device when

it is powered down.

2. Features and benefits

• Wide supply voltage range from 0.8 V to 3.6 V

• CMOS low power dissipation

• High noise immunity

• Overvoltage tolerant inputs to 3.6 V

• Low static power consumption; ICC = 0.9 μA (maximum)

• Latch-up performance exceeds 100 mA per JESD 78 Class II

• Low noise overshoot and undershoot < 10 of VCC

• IOFF circuitry provides partial Power-down mode operation

• Complies with JEDEC standards:

• JESD8-12 (0.8 V to 1.3 V)

• JESD8-11 (0.9 V to 1.65 V)

• JESD8-7 (1.2 V to 1.95 V)

• JESD8-5 (1.8 V to 2.7 V)

• JESD8C (2.7 V to 3.6 V)

• ESD protection:

• HBM JESD22-A114F Class 3A exceeds 5 kV

• MM JESD22-A115-A exceeds 200 V

• CDM JESD22-C101E exceeds 1 kV

• Multiple package options

• Specified from -40 °C to +85 °C and -40 °C to +125 °C