Low-power D-type flip-flop with set and reset; positive-edge trigger

文件：112.63 Kbytes 页数：23 Pages

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PHI

Low-power D-type flip-flop with set and reset; positive-edge trigger

文件：128.09 Kbytes 页数：24 Pages

恩XP

丝印：p74；Package：VSSOP8；Low-power D-type flip-flop with set and reset; positive-edge trigger

文件：243.99 Kbytes 页数：20 Pages

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Low-power D-type flip-flop with set and reset; positive-edge trigger

文件：128.09 Kbytes 页数：24 Pages

恩XP

Low-power D-type flip-flop with set and reset; positive-edge trigger

文件：112.63 Kbytes 页数：23 Pages

PHI

PHI

Low-power D-type flip-flop with set and reset; positive-edge trigger

文件：128.09 Kbytes 页数：24 Pages

恩XP

Low-power D-type flip-flop with set and reset; positive-edge trigger

文件：128.09 Kbytes 页数：24 Pages

恩XP

Low-power D-type flip-flop with set and reset; positive-edge trigger

文件：112.63 Kbytes 页数：23 Pages

PHI

PHI

Low-power D-type flip-flop with set and reset; positive-edge trigger

文件：243.99 Kbytes 页数：20 Pages

NEXPERIA

安世

Low-power D-type flip-flop with set and reset; positive-edge trigger

The 74AUP1G74-Q100 provides a low-power, low-voltage single positive-edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and complementary Q and Q outputs. The SD and RD are asynchronous active LOW inputs and operate independently of the clock input. • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n• Wide supply voltage range from 0.8 V to 3.6 V\n• High noise immunity\n• Complies with JEDEC standards:• JESD8-12 (0.8 V to 1.3 V)\n• JESD8-11 (0.9 V to 1.65 V)\n•;

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