Low-power 2-input OR-gate

1. General description The 74AUP1G32 is a single 2-input OR gate. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device i

文件：273.84 Kbytes 页数：18 Pages

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Low-power 2-input OR gate

文件：83.51 Kbytes 页数：16 Pages

PHI

PHI

SINGLE 2 INPUT POSITIVE OR GATE

文件：188 Kbytes 页数：11 Pages

DIODES

美台半导体

Single-gate

The Advanced Ultra Low Power (AUP) CMOS logic family is designed\nfor low power and extended battery life in portable applications.\n\nThe 74AUP1G32 is a single 2-input positive OR gate with a standard\npush-pull output designed for operation over a power supply range of\n0.8V to 3.6V. The device is •Advanced Ultra Low Power (AUP) CMOS•Supply Voltage Range from 0.8V to 3.6V•±4mA Output Drive at 3.0V•Low Static power consumption;

Diodes

美台半导体

Low-power 3-input OR-AND gate

1. General description The 74AUP1G3208 is a single 3-input OR-AND gate. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This de

文件：276.79 Kbytes 页数：18 Pages

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丝印：A2；Package：SOT886；Low-power 3-input OR-AND gate

1. General description The 74AUP1G3208 is a single 3-input OR-AND gate. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This de

文件：276.79 Kbytes 页数：18 Pages

NEXPERIA

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丝印：A2；Package：SOT1115；Low-power 3-input OR-AND gate

1. General description The 74AUP1G3208 is a single 3-input OR-AND gate. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This de

文件：276.79 Kbytes 页数：18 Pages

NEXPERIA

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丝印：A2；Package：SOT1202；Low-power 3-input OR-AND gate

1. General description The 74AUP1G3208 is a single 3-input OR-AND gate. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This de

文件：276.79 Kbytes 页数：18 Pages

NEXPERIA

安世

丝印：A2；Package：SOT363-2；Low-power 3-input OR-AND gate

1. General description The 74AUP1G3208 is a single 3-input OR-AND gate. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This de

文件：276.79 Kbytes 页数：18 Pages

NEXPERIA

安世

丝印：A2；Package：SOT1255-2；Low-power 3-input OR-AND gate

1. General description The 74AUP1G3208 is a single 3-input OR-AND gate. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This de

文件：276.79 Kbytes 页数：18 Pages

NEXPERIA

安世