Low-power Schmitt trigger

1. General description The 74AUP1G17 is a single buffer with Schmitt-trigger input. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitr

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NEXPERIA

安世

Low-power Schmitt-trigger buffer

文件：96.5 Kbytes 页数：20 Pages

PHI

PHI

SINGLE SCHMITT-TRIGGER BUFFER

文件：190.92 Kbytes 页数：11 Pages

DIODES

美台半导体

Low-power Schmitt trigger

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恩XP

Low Power Single Schmitt-Trigger Buffer

The 74AUP1G17 is a low power single Schmitt-trigger buffer and it operates supply voltage range from 0.8V to 3.6V. The device can keep very low static and dynamic power dissipation over the entire supply voltage range, so it can extend battery operation time and maintain good signal integrity. This ● Wide Supply Voltage Range: 0.8V to 3.6V● Inputs Accept Voltages Higher than the Supply Voltage● +4mA/-4mA Output Current● Low Quiescent Current: ICC = 0.1μA (TYP)● Low Dynamic Power Dissipation: CPD = 7.5pF at VCC = 3.3V (TYP)● Input with Schmitt-Trigger● Support Partial Power-Down Mode● -40℃ to +;

SGMICRO

圣邦股份

Single-gate

The Advanced Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications.\n\nThe AUP1G17 is a single 1-input Schmitt-trigger buffer gate with a push-pull output designed for operation over a power supply range of .8V to 3.6V. The device is ful •Advanced Ultra Low Power (AUP) CMOS•Supply Voltage Range from 0.8V to 3.6V•±4mA Output Drive at 3.0V•Low Static Power Consumption;

Diodes

美台半导体

Low-power D-type flip-flop with reset; positive-edge trigger

1. General description The 74AUP1G175 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), master reset (MR) inputs, and Q output. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-fl

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丝印：AT；Package：SOT886；Low-power D-type flip-flop with reset; positive-edge trigger

1. General description The 74AUP1G175 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), master reset (MR) inputs, and Q output. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-fl

文件：296.09 Kbytes 页数：21 Pages

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丝印：AT；Package：SOT1115；Low-power D-type flip-flop with reset; positive-edge trigger

1. General description The 74AUP1G175 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), master reset (MR) inputs, and Q output. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-fl

文件：296.09 Kbytes 页数：21 Pages

NEXPERIA

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丝印：AT；Package：SOT1202；Low-power D-type flip-flop with reset; positive-edge trigger

1. General description The 74AUP1G175 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), master reset (MR) inputs, and Q output. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-fl

文件：296.09 Kbytes 页数：21 Pages

NEXPERIA

安世