丝印：AT；Package：SOT363-2；Low-power D-type flip-flop with reset; positive-edge trigger

1. General description The 74AUP1G175 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), master reset (MR) inputs, and Q output. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-fl

文件：296.09 Kbytes 页数：21 Pages

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丝印：PJ；Package：SOT886；Low-power Schmitt trigger

1. General description The 74AUP1G17 is a single buffer with Schmitt-trigger input. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitr

文件：321.24 Kbytes 页数：24 Pages

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丝印：PJ；Package：SOT1115；Low-power Schmitt trigger

1. General description The 74AUP1G17 is a single buffer with Schmitt-trigger input. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitr

文件：321.24 Kbytes 页数：24 Pages

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丝印：PJ；Package：SOT1202；Low-power Schmitt trigger

1. General description The 74AUP1G17 is a single buffer with Schmitt-trigger input. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitr

文件：321.24 Kbytes 页数：24 Pages

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丝印：PJ；Package：SOT753；Low-power Schmitt trigger

1. General description The 74AUP1G17 is a single buffer with Schmitt-trigger input. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitr

文件：321.24 Kbytes 页数：24 Pages

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Low-power Schmitt trigger

Features » Wide supply voltage range from 0.8V 10 3.6V. « Inputs accept voltages up to 3.6 « lor supports partial-power-down mode » Low static power consumption; lcc=0.5A (Max.) » ESD Protection Exceeds JESD 22 ~2000-V Human-Body Model (A114-A) -200-V Machine Model (A115-A) ~1000-V Charged

文件：2.64141 Mbytes 页数：6 Pages

TECHPUBLIC

台舟电子

丝印：PJ；Package：SOT353-1；Low-power Schmitt trigger

1. General description The 74AUP1G17 is a single buffer with Schmitt-trigger input. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitr

文件：321.24 Kbytes 页数：24 Pages

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丝印：pJ；Package：TSSOP5；Low-power Schmitt trigger

1. General description The 74AUP1G17-Q100 is a single buffer with Schmitt-trigger input. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF cir

文件：247.18 Kbytes 页数：17 Pages

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丝印：PJ；Package：SOT1226-3；Low-power Schmitt trigger

1. General description The 74AUP1G17 is a single buffer with Schmitt-trigger input. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitr

文件：321.24 Kbytes 页数：24 Pages

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丝印：PJ；Package：SOT1269-2；Low-power Schmitt trigger

1. General description The 74AUP1G17 is a single buffer with Schmitt-trigger input. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitr

文件：321.24 Kbytes 页数：24 Pages

NEXPERIA

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