74ALVCH16952DGG数据手册Nexperia中文资料规格书

描述 Description

The 74ALVCH16952 consists of two sections, each containing a dual octal non-inverting registered transceiver. Two 8-bit back to back registers store data flowing in both directions between two bidirectional buses. Data applied to the inputs is entered and stored on the rising edge of the clock (nCPAB and nCPBA) provided that the clock enable (nCEAB and nCEBA) is LOW. The data is then present at the output buffers, but is only accessible when the output enable input (nOEAB and nOEBA) is LOW. Data flow from A inputs to B outputs is the same as for B inputs to A outputs.

特性 Features

• CMOS low-power consumption
• Multibyte flow-through pinout architecture
• Low inductance, multiple center power and ground pins for minimum noise and ground bounce
• Direct interface with TTL levels
• Output drive capability 50 Ω transmission lines at 85 °C
• Complies with JEDEC standard JESD8-B