74ALVCH16821DGG数据手册Nexperia中文资料规格书

描述 Description

The 74ALVCH16821 has two 10-bit, edge triggered registers, with each register coupled to a 3-state output buffer. The two sections of each register are controlled independently by the clock (nCP) and output enable (nOE) control gates.
Each register is fully edge triggered. The state of each nDn input, one set-up time before the Low-to-High clock transition, is transferred to the corresponding flip-flop’s nQn output.
When nOE is LOW, the data in the register appears at the outputs. When nOE is HIGH, the outputs are in high impedance OFF state. Operation of the nOE input does not affect the state of the flip-flops.
The 74ALVCH16821 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors.

特性 Features

• Wide supply voltage range from 1.2 V to 3.6 V
• CMOS low-power consumption
• Direct interface with TTL levels
• Current drive ± 24 mA at 3.0 V
• MULTIBYTE flow-through standard pin-out architecture
• Low inductance multiple VCC and GND pins for minimum noise and ground bounce
• Output drive capability 50 Ω transmission lines at 85°C
• All data inputs have bushold
• Complies with JEDEC standard no. 8-1A
• Complies with JEDEC standards:
• JESD8-5 (2.3 V to 2.7 V)
• JESD8B/JESD36 (2.7 V to 3.6 V)

• ESD protection:
• HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V
• CDM JESD22-C101E exceeds 1000 V