74ALVCH16500DGG数据手册Nexperia中文资料规格书

描述 Description

The 74ALVCH16500 is a high-performance CMOS product. This device is an 18-bit universal transceiver featuring non-inverting 3-State bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA) latch enable (LEAB and LEBA)and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is High. When LEAB is Low, the A data is latched if CPAB is held at a High or Low logic level. If LEAB is Low, the A-bus data is stored in the latch/flip-flop on the High-to-Low transition of CPAB. When OEAB is High, the outputs are active. When OEAB is Low, the outputs are in the high-impedance state.
Data flow for B-to-A is similar to that of A-to-B but uses OEBA LEBA and CPBA. The output enables are complimentary (OEAB is active High, and OEBA is active Low).
To ensure the high impedance state during power up or power down, OEBA should be tied to VCC through a pullup resistor and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

特性 Features

• Complies with JEDEC standard no. 8-1A
• CMOS low power consumption
• Direct interface with TTL levels
• Current drive ± 24 mA at 3.0 V
• All inputs have bushold circuitry
• Output drive capability 50Ω transmission lines @ 85°C
• MULTIBYTE™™ flow-through standard pin-out architecture
• Low inductance multiple VCC and ground pins for minimum noise and ground bounce