74ALVCH16501DGG数据手册Nexperia中文资料规格书

描述 Description

The 74ALVCH16501 is an 18-bit transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CPAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A-bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CPAB. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the outputs are in the high-impedance state.
Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. The output enables are complimentary (OEAB is active HIGH, and OEBA is active LOW.
To ensure the high-impedance state during power-up or power-down, OEBA should be tied to VCC through a pull-up resistor and OEAB should be tied to GND through a pull-down resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver.
Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

特性 Features

• Wide supply voltage range from 1.2 V to 3.6 V
• Complies with JEDEC standard JESD8-B
• CMOS low power consumption
• Direct interface with TTL levels
• Current drive ±24 mA at VCC = 3.0 V
• Universal bus transceiver with D-type latches and D-type flip-flops capable of operating in transparent, latched or clocked mode
• All inputs have bus hold circuitry
• Output drive capability 50 Ω transmission lines at 85 °C
• 3-state non-inverting outputs for bus-oriented applications