74ALVCH16843DGG中文资料18-bit bus-interface D-type latch; 3-state数据手册Nexperia规格书

描述 Description

The 74ALVCH16843 has two 9-bit D-type latch featuring separate D-type inputs for each latch and 3-State outputs for bus oriented applications. The two sections of each register are controlled independently by the latch enable (nLE) clear (nCLR) preset (nPRE) and output enable (nOE) control gates.
When nOE is LOW, the data in the registers appear at the outputs. When nOE is HIGH, the outputs are in the high impedance OFF state. Operation of the nOE input does not affect the state of the flip-flops.
The 74ALVCH16843 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors.

特性 Features

• Wide supply voltage range of 1.2 V to 3.6 V
• Complies with JEDEC standard no. 8-1A.
• CMOS low power consumption
• Direct interface with TTL levels
• Current drive ±24 mA at 3.0 V
• MULTIBYTE™™ flow-through standard pin-out architecture
• Low inductance multiple VCC and GND pins for minimum noise and ground bounce
• All data inputs have bus hold
• Output drive capability 50 Ω transmission lines @ 85 °C