74ALVCH16827DGG数据手册Nexperia中文资料规格书

描述 Description

The 74ALVCH16827 is a 20-bit non-inverting buffer/driver with 3-State outputs for bus oriented applications.
The 74ALVCH16827 consists of two 10-bit sections with separate output enable signals. For either 10-bit buffer section, the two output enable (1OE1 and 1OE2 or 2OE1 and 2OE2) inputs must both be active. If either output enable input is high, the outputs of that 10-bit buffer section are in high impedance state.
The 74ALVCH16827 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors.

特性 Features

• Wide supply voltage range of 1.2V to 3.6V
• Complies with JEDEC standard no. 8-1A
• Wide supply voltage range of 1.2V to 3.6V
• CMOS low power consumption
• Direct interface with TTL levels
• Universal bus transceiver with D-type latches and D-type flip-flops capable of operating in transparent, latched, clocked or clocked-enabled mode.
• MULTIBYTE™ flow-through standard pin-out architecture
• Low inductance multiple VCC and GND pins for minimum noise and ground bounce
• Current drive ±24 mA at 3.0 V
• All inputs have bus hold circuitry
• Output drive capability 50 Ω transmission lines @ 85°C
• 3-State non-inverting outputs for bus oriented applications