74ALVCH16825DGG中文资料18-bit buffer/driver (3-State)数据手册Nexperia规格书

描述 Description

The 74ALVCH16825 is an 18-bit non-inverting buffer/driver with 3-State outputs for bus-oriented applications.
The 74ALVCH16825 consists of two 9-bit sections with separate output enable signals. For either 9-bit buffer section, the two output enable (1OE1 and 1OE2 or 2OE1 and 2OE2) inputs must both be LOW for corresponding D outputs to be active. If either output enable input is HIGH, the outputs of that 9-buffer section are in the high impedance state.
The 74ALVCH16825 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors.

特性 Features

• Wide supply Voltage range of 1.2V to 3.6V
• Complies with JEDEC standard no. 8-1A.
• CMOS low power consumption
• Direct interface with TTL levels
• Current drive ± 24 mA at 3.0 V
• MULTIBYTE TM flow-through standard pin-out architecture
• Low inductance multiple Vcc and GND pins for minimum noise and ground bounce
• All data inputs have bus hold
• Output drive capability 50W transmission lines @ 85 °C