丝印：320AIC14KI；Package：TSSOP(DBT)；LOW-POWER, HIGHLY-INTEGRATED, PROGRAMMABLE 16-Bit, 26-KSPS MONO CODEC

FEATURES · Mono 16-Bit Oversampling Sigma-Delta A/D Converter · Mono 16-Bit Oversampling Sigma-Delta D/A Converter · Support Maximum Master Clock of 100 MHz to Allow the DSP Output Clock to be Used as a Master Clock · Selectable FIR/IIR Filter With Bypassing Option · Programmable Samplin

文件：2.12866 Mbytes 页数：66 Pages

TI

德州仪器

丝印：320AIC14KI；Package：TSSOP(DBT)；LOW-POWER, HIGHLY-INTEGRATED, PROGRAMMABLE 16-Bit, 26-KSPS MONO CODEC

FEATURES · Mono 16-Bit Oversampling Sigma-Delta A/D Converter · Mono 16-Bit Oversampling Sigma-Delta D/A Converter · Support Maximum Master Clock of 100 MHz to Allow the DSP Output Clock to be Used as a Master Clock · Selectable FIR/IIR Filter With Bypassing Option · Programmable Samplin

文件：2.12866 Mbytes 页数：66 Pages

TI

德州仪器

丝印：320AIC14KI；Package：TSSOP(DBT)；LOW-POWER, HIGHLY-INTEGRATED, PROGRAMMABLE 16-Bit, 26-KSPS MONO CODEC

FEATURES · Mono 16-Bit Oversampling Sigma-Delta A/D Converter · Mono 16-Bit Oversampling Sigma-Delta D/A Converter · Support Maximum Master Clock of 100 MHz to Allow the DSP Output Clock to be Used as a Master Clock · Selectable FIR/IIR Filter With Bypassing Option · Programmable Samplin

文件：2.12866 Mbytes 页数：66 Pages

TI

德州仪器

丝印：320AIC14KI；Package：TSSOP(DBT)；LOW-POWER, HIGHLY-INTEGRATED, PROGRAMMABLE 16-Bit, 26-KSPS MONO CODEC

FEATURES · Mono 16-Bit Oversampling Sigma-Delta A/D Converter · Mono 16-Bit Oversampling Sigma-Delta D/A Converter · Support Maximum Master Clock of 100 MHz to Allow the DSP Output Clock to be Used as a Master Clock · Selectable FIR/IIR Filter With Bypassing Option · Programmable Samplin

文件：2.12866 Mbytes 页数：66 Pages

TI

德州仪器

丝印：320AIC14KI；Package：TSSOP(DBT)；LOW-POWER, HIGHLY-INTEGRATED, PROGRAMMABLE 16-Bit, 26-KSPS MONO CODEC

FEATURES · Mono 16-Bit Oversampling Sigma-Delta A/D Converter · Mono 16-Bit Oversampling Sigma-Delta D/A Converter · Support Maximum Master Clock of 100 MHz to Allow the DSP Output Clock to be Used as a Master Clock · Selectable FIR/IIR Filter With Bypassing Option · Programmable Samplin

文件：2.12866 Mbytes 页数：66 Pages

TI

德州仪器

丝印：320AIC15I；Package：TSSOP；SMARTDM™ Low-Power, Low-Voltage, 1.1-V to 3.6-V 1/0, 16-Bit, 26-KSPS Codec

1.1 Description The TLV320AIC15 implements the smart time division multiplexed serial port (SMARTDM). This is TI’s design innovation to optimize DSP performance with its most advanced synchronous serial port in TDM format for glue-free interface to popular DSPs (i.e., C5x, C6x) and microcontro

文件：684.32 Kbytes 页数：56 Pages

TI

德州仪器

丝印：320AIC15I；Package：TSSOP；SMARTDM™ Low-Power, Low-Voltage, 1.1-V to 3.6-V 1/0, 16-Bit, 26-KSPS Codec

1.1 Description The TLV320AIC15 implements the smart time division multiplexed serial port (SMARTDM). This is TI’s design innovation to optimize DSP performance with its most advanced synchronous serial port in TDM format for glue-free interface to popular DSPs (i.e., C5x, C6x) and microcontro

文件：684.32 Kbytes 页数：56 Pages

TI

德州仪器

丝印：320AIC20C；Package：TQFP(PFB)；Low-Power, Highly-Integrated, Programmable 16-Bit, 26-KSPS, Dual-Channel CODEC

FEATURES · Stereo 16-Bit Oversampling Sigma-Delta A/D Converter · Stereo 16-Bit Oversampling Sigma-Delta D/A Converter · Support Maximum Master Clock of 100 MHz to Allow DSPs Output Clock to be Used as a Master Clock · Selectable FIR/IIR Filter With Bypassing Option · Programmable Sampli

文件：1.24218 Mbytes 页数：59 Pages

TI

德州仪器

丝印：320AIC20C；Package：TQFP(PFB)；Low-Power, Highly-Integrated, Programmable 16-Bit, 26-KSPS, Dual-Channel CODEC

FEATURES · Stereo 16-Bit Oversampling Sigma-Delta A/D Converter · Stereo 16-Bit Oversampling Sigma-Delta D/A Converter · Support Maximum Master Clock of 100 MHz to Allow DSPs Output Clock to be Used as a Master Clock · Selectable FIR/IIR Filter With Bypassing Option · Programmable Sampli

文件：1.24218 Mbytes 页数：59 Pages

TI

德州仪器

丝印：320AIC20I；Package：TQFP(PFB)；Low-Power, Highly-Integrated, Programmable 16-Bit, 26-KSPS, Dual-Channel CODEC

FEATURES · Stereo 16-Bit Oversampling Sigma-Delta A/D Converter · Stereo 16-Bit Oversampling Sigma-Delta D/A Converter · Support Maximum Master Clock of 100 MHz to Allow DSPs Output Clock to be Used as a Master Clock · Selectable FIR/IIR Filter With Bypassing Option · Programmable Sampli

文件：1.24218 Mbytes 页数：59 Pages

TI

德州仪器