丝印：V74；Package：SOT765-1；Single D-type flip-flop with set and reset; positive edge trigger

1. General description The 74LVC1G74 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transi

文件：290.66 Kbytes 页数：19 Pages

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安世安世半导体(中国)有限公司

丝印：V74；Package：SOT505-2；Single D-type flip-flop with set and reset; positive edge trigger

1. General description The 74LVC1G74 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transi

文件：290.66 Kbytes 页数：19 Pages

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

丝印：V74；Package：SOT833-1；Single D-type flip-flop with set and reset; positive edge trigger

1. General description The 74LVC1G74 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transi

文件：290.66 Kbytes 页数：19 Pages

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

丝印：V74；Package：SOT765-1；Single D-type flip-flop with set and reset; positive edge trigger

1. General description The 74LVC2G74 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transi

文件：278.15 Kbytes 页数：18 Pages

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

丝印：V74；Package：SOT505-2；Single D-type flip-flop with set and reset; positive edge trigger

1. General description The 74LVC2G74 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transi

文件：278.15 Kbytes 页数：18 Pages

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

丝印：V74；Package：SOT833-1；Single D-type flip-flop with set and reset; positive edge trigger

1. General description The 74LVC2G74 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transi

文件：278.15 Kbytes 页数：18 Pages

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

丝印：V74；HETERO JUNCTION FIELD EFFECT TRANSISTOR

FEATURES • Super low noise figure & associated gain: NF = 0.75 TYP., Ga = 12 dB TYP. @ f = 12 GHz NF = 0.4 TYP., Ga = 16 dB TYP. @ f = 4 GHz • 6-pin super minimold package • Gate width: Wg = 160 mm

文件：206.81 Kbytes 页数：10 Pages

RENESAS

瑞萨

丝印：V74；Package：VSSOP8；Single D-type flip-flop with set and reset; positive edge trigger

文件：245.63 Kbytes 页数：16 Pages

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

丝印：V74；Package：TSSOP8；Single D-type flip-flop with set and reset; positive edge trigger

文件：245.63 Kbytes 页数：16 Pages

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

丝印：V74；Package：XSON8；Single D-type flip-flop with set and reset; positive edge trigger

文件：245.63 Kbytes 页数：16 Pages

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司