Single D-type flip-flop with set and reset; positive edge trigger

General description The 74LVC1G74 is a single positive edge triggered D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (SD) and reset (RD) inputs, and complementary Q and Q outputs. This device is fully specified for partial power-down applications using IOFF.

文件：103.94 Kbytes 页数：19 Pages

恩XP

Single D-type flip-flop with set and reset; positive edge trigger

DESCRIPTION The 74LVC1G74 is a high-performance, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The 74LVC1G74 is a single positive edge triggered D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (SD) and (RD) inputs, and comp

文件：112.64 Kbytes 页数：19 Pages

PHI

PHI

丝印：V74；Package：SOT765-1；Single D-type flip-flop with set and reset; positive edge trigger

1. General description The 74LVC1G74 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transi

文件：290.66 Kbytes 页数：19 Pages

NEXPERIA

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Single D-type flip-flop with set and reset; positive edge trigger

文件：166.02 Kbytes 页数：25 Pages

PHI

PHI

Single D-type flip-flop with set and reset; positive edge trigger

文件：202.57 Kbytes 页数：25 Pages

恩XP

Single D-type flip-flop with set and reset; positive edge trigger

文件：549.89 Kbytes 页数：21 Pages

恩XP

Single D-type flip-flop with set and reset; positive edge trigger

文件：549.89 Kbytes 页数：21 Pages

恩XP

Single D-type flip-flop with set and reset; positive edge trigger

文件：299.15 Kbytes 页数：25 Pages

恩XP

丝印：V74；Package：VSSOP8；Single D-type flip-flop with set and reset; positive edge trigger

文件：245.63 Kbytes 页数：16 Pages

NEXPERIA

安世

Single D-type flip-flop with set and reset; positive-edge trigger

The 74LVC1G74 is a single positive edge triggered D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (SD) and reset (RD) inputs, and complementary Q and Q outputs.\n This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables th • Wide supply voltage range from 1.65 V to 5.5 V\n• 5 V tolerant inputs for interfacing with 5 V logic\n• High noise immunity\n• Complies with JEDEC standard:• JESD8-7 (1.65 V to 1.95 V)\n• JESD8-5 (2.3 V to 2.7 V)\n• JESD8-B/JESD36 (2.7 V to 3.6 V)\n\n• ESD protection:• HBM JESD22-A114F exceeds 200;

Nexperia

安世