288M-BIT Low Latency DRAM Common I/O

Features • SRAM-type interface • Double-data-rate architecture • PLL circuitry • Cycle time: 2.5 ns @ tRC = 20 ns 3.3 ns @ tRC = 20 ns • Non-multiplexed addresses • Multiplexing option is available. • Data mask for WRITE commands • Differential input clocks (CK and CK#) • Differential in

文件：862.5 Kbytes 页数：50 Pages

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288M-BIT Low Laten cy DRAM Common I/O

Features • SRAM-type interface • Double-data-rate architecture • PLL circuitry • Cycle time: 1.875 ns @ tRC = 15 ns 2.5 ns @ tRC = 15 ns 2.5 ns @ tRC = 20 ns 3.3 ns @ tRC = 20 ns • Non-multiplexed addresses • Multiplexing option is available. • Data mask for WRITE commands • Differentia

文件：1.10465 Mbytes 页数：53 Pages

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SOT563

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上传：深圳市正纳电子有限公司

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HTSSOT16

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上传：深圳市正纳电子有限公司

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HTSSOP16

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上传：深圳市正纳电子有限公司