SY10E151数据手册集成电路（IC）的触发器规格书PDF

描述 Description

The SY10/100E151 offer 6 edge-triggered, high-speed, master-slave D-type flip-flops with differential outputs, designed for use in new, high-performance ECL systems.The two external clock signals (CLK1, CLK2) are gated through a logical OR operation before use as clocking control for the flip-flops. Data is clocked into the flip-flops on the rising edge of either CLK1 or CLK2 (or both). When both CLK1 andCLK2 are at a logic LOW, data enters the master and is transferred to the slave when either CLK1 or CLK2 (or both) go HIGH.The MR (Master Reset) signal operates asynchronously to make all Q outputs go to a logic LOW.rential 10K ECL logic can interface directly into the SY100EP14U inputs.
The SY100EP14U is part of Micrel's high-speed clock synchronization family. For applications that require a different I/O combination, choose from a comprehensive product line of high-speed, low-skew fanout buffers, translators, and clock generators.

特性 Features

·1100MHz toggle frequency
·Extended 100E VEE range of -4.2V to -5.46V
·Differential outputs
·Asynchronous Master Reset
·Dual clocks
·Fully compatible with industry standard 10KH, 100K ECL levels
·Internal 75KΩ input pulldown resistors
·Fully compatible with Motorola MC10E/100E151
·Available in 28-pin PLCC package

简介

SY10E151属于集成电路（IC）的触发器。由制造生产的SY10E151触发器触发器是能够存储单个逻辑状态或信息“位”的基本数字存储器件。这些器件至少有两个输入；一个或多个用于传递要存储的数据，另一个用于指示存储该数据的时间点。不同的触发器类型，例如 D（延迟）、SR（置位复位）和 JK，对提供给其输入的信号有不同的响应，可用于实现不同的逻辑功能。这些器件与锁存器的不同之处在于它们是边缘敏感器件，其保持的逻辑状态仅在接收到有效时钟信号时才会改变。