SY100S815数据手册集成电路（IC）的专用逻辑器件规格书PDF

描述 Description

The SY100S815 is a low skew 1-to-4 PECL differential driver designed for clock distribution in new, highperformance PECL systems. It accepts either a PECL clock input or a TTL input by using the TTL enable pin TEN. When the TTL enable pin is HIGH, the TTL input is enabled and the PECL input is disabled. When the enable pin is set LOW, the TTL input is disabled and the PECL input is enabled.The device is specifically designed and produced for low skew. The interconnect scheme and metal layout are carefully optimized for minimal gate-to-gate skew within the device. Wafer characterization and process control ensure consistent distribution of propagation delay from lot to lot. Since the S815 shares a common set of \"basic\" processing with the other members of the ECLinPS family, wafer characterization at the point of device personalization allows for tighter control of parameters, incuding propagation delay.To ensure that the skew specification is met, it is necessary that both sides of the differential output are terminated into 50Ω, even if only one side is being used. In most applications, all nine differential pairs will be used and, therefore, terminated. In the case where fewer than nine pairs are used, it is necessary to terminate at least the output pairs on the same package side (i.e. sharing the same VCCO as the pair(s) being used on that side) in order to maintain minimum skew.

特性 Features

·Quad PECL version of popular ECLinPS E111
·Low skew
·Guaranteed skew spec
·TTL enable input
·Selectable TTL or PECL clock input
·Single +5V supply
·Differential internal design
·PECL I/O fully compatible with industry standard
·Internal 75kΩ PECL input pull-down resistors
·Available in 16-pin SOIC package

简介

SY100S815属于集成电路（IC）的专用逻辑器件。由制造生产的SY100S815专用逻辑器件专用逻辑 IC 设计提供应用特定的逻辑输出类型，例如 BCD 速率倍增、可寻址扫描端口、总线终端阵列、CML 驱动器、比较器、ABT 扫描测试、二进制全加法器、互补对加逆变器、可配置缓冲器、触点颤动消除器、晶体振荡器、延迟元件、差分接收器、LVTTL 到 GTLP 收发器、存储器解码器、电源良好检测器和分频器。