SY10E143中文资料Flip Flops, Registers Products数据手册Microchip规格书

描述 Description

The SY10/100E143 are high-speed 9-bit hold registers designed for use in new, high-performance ECL systems. The E143 can hold current data or load new data. The nine inputs, D0-D8, accept parallel input data.The SEL (Select) control pin serves to determine the mode of operation; either HOLD or LOAD. The input data has to meet the set-up time before being clocked into the nine input registers on the rising edge of CLK1 or CLK2.The MR (Master Reset) control signal asynchronously resets all nine registers to a logic LOW when a logic HIGH is applied to MR.The E143 is designed for applications requiring highspeed registers, pipeline registers, synchronous operation, and is also suitable for byte-wide parity.To ensure that the tight skew specification is met it is necessary that both sides of the differential output are terminated into 50Ω, even if only one side is being used. In most applications, all nine differential pairs will be used and therefore terminated. In the case where fewer that nine pairs are used, it is necessary to terminate at least the output pairs on the same package side as the pair(s) being used on that side, in order to maintain minimum skew. Failure to do this will result in small degradations of propagation delay (on the order of 10-20ps) of the output(s) being used which, while not being catastrophic to most designs, will mean a loss of skew margin.
The E111AE/LE, as with most other ECL devices, can be operated from a positive VCC supply in PECL mode. This allows the E111AE/LE to be used for high performance clock distribution in +5V/+3.3V systems. Designers can take advantage of the E111AE/LE's performance to distribute low skew clocks across the backplane or the board. In a PECL environment, series or Thevenin line terminations are typically used as they require no additional power supplies. For systems incorporating GTL, parallel termination offers the lowest power by taking advantage of the 1.2V supply as terminating voltage.

特性 Features

·700MHz min. operating frequency
·Extended 100E VEE range of -4.2V to -5.5V
·9 bits wide for byte-parity applications
·Asynchronous Master Reset
·Dual clocks
·Fully compatible with industry standard 10KH, 100K ECL levels
·Internal 75kΩ input pulldown resistors
·Fully compatible with Motorola MC10E/100E143
·Available in 28-pin PLCC package

简介

SY10E143属于集成电路（IC）的移位寄存器。由制造生产的SY10E143移位寄存器移位寄存器是低级逻辑器件，通常用于在串行和并行方式之间转换数字逻辑信号形式的数据，或在数字字内移动数据位的位置。移位寄存器通常使用集成到一个设备中的一组触发器来实现，常用于集成度更高的逻辑器件，但仍可用于 I/O 扩展等应用，在这些应用中离散形式的函数可能会非常有用。