RC32

Molded Metal Film Resistors

RC32

Precision chip resistors

RC32012A

FemtoClock Jitter Attenuator and Clock Generator

Features ▪Canbeconfiguredasclockgeneratororjitter attenuator/synchronizer ▪Lowpower,lessthan1.2Wtypical ▪Lowjitter,lessthan100fs-RMS ▪CompliantwithITU-TG.8262andG.8262.1 option1and2forsynchronousEthernet EquipmentClock(EEC/eEEC)withoutdegrading outputji

RC32012A-001

RC32012A-001 Custom Configuration

ThisdatasheetaddendumistobeusedinconjunctionwiththeoverallRC32012Adatasheet.Thisaddendum indicatestheregistersettingsthatarepre-configuredintheinternalOne-TimeProgrammable(OTP)memoryof thedevicebyRenesas.Theseregistersettingsrepresentthedefaultvaluesthere

RC32112A

FemtoClock Jitter Attenuator and Clock Generator

Features ▪Canbeconfiguredasclockgeneratororjitter attenuator/synchronizer ▪Lowpower,lessthan1.4Wtypical ▪Lowjitter,lessthan100fs-RMS ▪CompliantwithITU-TG.8262andG.8262.1 option1and2forsynchronousEthernet EquipmentClock(EEC/eEEC)withoutdegrading outputji

RC32112A

FemtoClock Jitter Attenuator or Clock Generator; • Two timing channels and six independent frequency domains\n• Output jitter below 100fs RMS\n• Digital PLLs (DPLLs) lock to any frequency from 0.5kHz to 1GHz\n• DPLLs / Digitally Controlled Oscillators (DCOs) generate any frequency from 0.5Hz to 1GHz\n• DCO outputs can be aligned in phase and frequency with the outputs of any DPLL or DCO\n• Can be used as a jitter attenuator, clock generator, or synchronizer\n• Reference monitors qualify/disqualify references depending on LOS, activity, frequency monitoring and/or LOS input pins\n• Automatic reference selection state machines select the active reference for each DPLL based on the reference monitors, priority tables, revertive / non-revertive and other programmable settings\n• Device requires a crystal oscillator or fundamental-mode crystal: 25MHz to 54MHz\n• The device can configure itself automatically after reset via:• Internal Customer-programmable One-Time Programmable memory\n• Standard external I2C EPROM via separate I2C Master Port\n;

The RC32112A regenerates and distributes ultra-low jitter clock outputs and features up to 6 independent frequency domains that can be either locked to the external reference clock or locked to a free-run crystal or oscillator. Digital PLLs (DPLLs) support hitless reference switching between references from redundant timing sources. The device supports multiple independent timing channels for: IEEE 1588 clock synthesis; SyncE clock generation; jitter attenuation and radio clock generation including SYSREF generation for converters. Input-to-input, input-to-output and output-to-output phase skew can all be precisely managed.  The device outputs ultra-low-jitter clocks that can directly synchronize SERDES running at up to 56Gbps; as well as CPRI/OBSAI, SONET/SDH ADC/DAC. The device is ideal for use in 100G/200G/400G/800G telecom switch line cards, fabric cards and wireless small cell applications.

RC32336

IDTTM InterpriseTM Integrated Communications Processor

DeviceOverview TheRC32336deviceisamemberoftheIDT™Interprise™familyof integratedcommunicationsprocessors.Itprovidesaneffectivesolution forsmalloffice/homeoffice(SOHO)applicationsincludinggatewaysand bothsingle-bandanddual-bandwirelessaccesspoints.Featuringa M

RC32365

IDTTM InterpriseTM Integrated Communications Processor

DeviceOverview TheRC32365deviceisamemberoftheIDT™Interprise™familyof integratedcommunicationsprocessors.Thisdeviceisdesignedto addressarangeofcommunicationsapplicationsthatrequiretheefficient processingofIPSecalgorithms.Theseapplicationsincludegateways, wire

RC32434

IDTTM InterpriseTM Integrated Communications Processor

DeviceOverview TheRC32434isamemberoftheIDT™Interprise™familyofPCI integratedcommunicationsprocessors.Itincorporatesahighperformance CPUcoreandanumberofon-chipperipherals.Theintegrated processorisdesignedtotransferinformationfromI/Omodulestomain memorywit

RC32504A

FemtoClock®2 Sub-100fs Universal Frequency Translator

Features •Jitterbelow100fsRMS(10kHzto20MHz) •CompliantwithITU-TG.8262forsynchronous Ethernet/OTN(EEC/OEC)andITU-TG.8262.1for enhancedsynchronousEthernet/OTN (eEEC/eOEC) •PLLcoreconsistsoffractional-feedbackAnalog PLL(APLL)whichcanoptionallybesteeredbya Dig