FemtoClock®2 Sub-100fs Universal Frequency Translator

Features • Jitter below 100fs RMS (10kHz to 20MHz) • Compliant with ITU-T G.8262 for synchronous Ethernet/OTN (EEC/OEC) and ITU-T G.8262.1 for enhanced synchronous Ethernet/OTN (eEEC/eOEC) • PLL core consists of fractional-feedback Analog PLL (APLL) which can optionally be steered by a Dig

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FemtoClock®2 Jitter Attenuator or Clock Generator

The RC32504A is a small, low-power timing component designed to be placed immediately adjacent to a PHY, switch, ASIC or FPGA that requires several reference clocks with jitter performance less than 100fs. The RC32504A can act as a frequency synthesizer to locally generate the reference clock, a jit • Jitter below 100fs RMS (10kHz to 20MHz)\n• Compliant with ITU-T G.8262 for synchronous Ethernet/OTN (EEC/OEC) and ITU-T G.8262.1 for enhanced synchronous Ethernet/OTN (eEEC/eOEC)\n• PLL core consists of fractional-feedback Analog PLL (APLL) which can optionally be steered by a Digital PLL (DPLL)• ;

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Package：24-WFQFN 裸露焊盘；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 类别：集成电路（IC） 时钟发生器，PLL，频率合成器 描述：FEMTOCLOCK 2 SYNTHESIZER \u0026 JITTE

Renesas Electronics America Inc

包装：散装 功能：频率转换器 类别：开发板，套件，编程器 评估和演示板及套件 描述：FEMTOCLOCK 2 EVALUATION KIT

Renesas Electronics America Inc