RC32012A集成电路（IC）的时钟发生器PLL频率合成器规格书PDF中文资料

特性 Features

▪ Can be configured as clock generator or jitter

attenuator/synchronizer

▪ Low power, less than 1.2W typical

▪ Low jitter, less than 100 fs-RMS

▪ Compliant with ITU-T G.8262 and G.8262.1

option 1 and 2 for synchronous Ethernet

Equipment Clock (EEC/eEEC) without degrading

output jitter

▪ PCIe Gen 1-6 CC, SRIS and SRNS support

▪ Jitter attenuation with programmable loop

bandwidth from 0.1Hz to 12kHz

▪ Up to four fractional output dividers and 12 integer

output dividers

• Each fractional output divider can be slaved with

DPLL or SYS-DPLL or free-run locked to APLL

▪ DPLL can be configured as DCO and each

fractional output divider can be configured as NCO

or DCO

▪ Combo bus allows frequency sharing between

DPLL, System DPLL, and each of the four

fractional output dividers

▪ LVCMOS, LVPECL, LVDS, HCSL, CML, SSTL,

HSTL output modes supported with programmable

output swing and common mode voltage

▪ JESD204B/C support on differential or single

ended outputs with DC-coupling or AC-coupling

▪ Up to seven single-ended or two differential clock

inputs, one crystal/XO input, and one

XO/TCXO/OCXO input

▪ Up to nine GPIO pins programmable to device

select or system monitor options

▪ Supports 1MHz I2C, 400kHz SMBus, or 50MHz

SPI serial port

▪ Internal non-volatile memory (up to 16 different

configurations), or external serial I2C EEPROM

provide default device settings on power-up.

▪ 2.5V and 3.3V core and 1.8V, 2.5V, and 3.3V

output operation

▪ -40° to +85°C industrial temperature operation