RC31008AQDDGL2KD0中文资料瑞萨数据手册PDF规格书

Features

▪ 169fs RMS typical phase jitter

▪ PCIe® Gen6 Common Clock (CC) 27fs RMS

▪ Compliant with ITU-T G.8262 and G.8262.1 for

synchronous Ethernet Equipment Clock

(EEC/eEEC)

▪ Jitter attenuation with programmable loop

bandwidth from 0.1Hz to 12kHz

▪ 1kHz to 650MHz LVDS/LP-HCSL outputs

▪ 1kHz to 200MHz LVCMOS outputs

▪ Simple AC-coupling to LVPECL and CML

▪ Integrated 100 and 85 LP-HCSL terminations

▪ JESD204B/C support on differential or singleended

outputs with DC-coupling or AC-coupling

▪ Up to four single-ended or two differential clock

inputs; one crystal/TCXO/OCXO input

▪ Programmable General Purpose Inputs (GPI × 4)

and General Purpose Input/Outputs (GPIO × 5)

▪ 1MHz I2C, 400kHz SMBus, or 20MHz SPI support

Configuration via internal One-Time Programmable

(OTP) memory (up to 27 different configurations),

serial interface, or external I2C EEPROM.

▪ Factory programmable internal OTP

▪ 1.8V, 2.5V, 3.3V, -40° to +85°C operation