Si Reverse, low current, 5 - 65MHz, 40.3dB typ. Gain @ 65MHz, 160mA max. @ 24VDC

DESCRIPTION • Hybrid reverse amplifier employing silicon die FEATURES • Excellent linearity • Superior return loss performance • Extremely low distortion • Optimal reliability • Low noise • Unconditionally stable under all terminations APPLICATION • 5 to 65 MHz CATV amplifier for reverse

文件：129.729 Kbytes 页数：4 Pages

PDI

CAN Controller

▪ Protocol : ISO 11898-1 compliant (standard and extended frames) ▪ Reception − Data frame and remote frame can be received. − Selectable receiving ID format. (only standard ID, only extended ID, or bothIDs) − Programmable one-shot reception function. − Selectable from overwrite mode (messa

文件：141.09 Kbytes 页数：1 Pages

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CAN FD Controller Multi-channel type

This IP is CAN FD controller that is compliant with ISO 11898-1 (2015) Specifications. It embeds multiple CAN channels. 2,4,6 and 8 channel version are available. Each CAN channel can be configurable to CAN FD or classic CAN and transmits and receives both ID formats of messages, namely the sta

文件：142.08 Kbytes 页数：2 Pages

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CAN FD Controller Single-channel type

This IP is CAN FD one channel version controller that is compliant with ISO 11898-1 (2015) Specifications. This CAN module embeds single CAN channel. This CAN module can be configurable to CAN FD or classic CAN, transmits and receives both ID formats of messages, namely the standard identifier

文件：123.1 Kbytes 页数：2 Pages

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LVDS I/O Buffer

The LVDS I/O has driver and receiver of TSMC 16, 22, 28, 40nm and Samsung 14nm process. - Support LVDS specification is TIA/EIA-644-A. - LVDS driver and receiver support data rates up to 600Mbps to 1Gbps. - ESD, LatchUp compliant with AEC-Q100 for automotive. - Power supplies 1.8V±0.15V for IO

文件：121.25 Kbytes 页数：1 Pages

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32-bit RISC CPU IP

▪ 32-bit internal data bus ▪ General purpose register file: − 16 32-bit general-purpose registers (and 8 32-bit shadow registers) − Seven 32-bit control registers − Four 32-bit system registers ▪ RISC type instruction set (with upward compatibility with SH-1, SH-2, SH-3, SH-4): − Instructi

文件：189.89 Kbytes 页数：1 Pages

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General PWM Timer

32 bits timer counter x 8 channels - Counter operation(Saw-wave and Triangle-wave) - Waveform output by compare match(A/B per channel) - Captures counter value by input trigger 3-phase PWM wave generator for brushless DC motor - PWM output for chopper - Level output

文件：138.46 Kbytes 页数：1 Pages

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SRAM IP

Remarkable Features of Renesas SRAM and TCAM IP. SRAM IP Portfolio ▪ Small area − By optimizing the peripheral circuit of memory, particularly small area is realized. ▪ Low power − Support low leak retention mode (Resume Standby) and power off mode (Shut down). ▪ IDM-oriented design quality

文件：148.79 Kbytes 页数：1 Pages

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Embedded TCAM IP

KEY FEATURES OF TCAM - TCAM searches for data that matches the input value in one cycle from all information stored in the memory. - If there are multiple matching data, find all of them Also, by adding a priority encoder, it is possible to select one from multiple matching data. - The search

文件：267.13 Kbytes 页数：2 Pages

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PCI Express 5.0 Link Controller

AMBA® AXI interface • Conforming to AMBA® AXI Protocol v1.0 Specification ARM IHI 0022B • Interface: Master/Slave • Endian: Little • Bus Width: 128 bits • DMAC functions are provided PCIe specification • Conforming to PCI Express Base Specification 5.0 • Supports PCIe1: 2.5[GT/s] PCIe2

文件：119.59 Kbytes 页数：1 Pages

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