MIPI CSI-2 Receiver IP Core

• Compliant with Specification for Camera Serial Interface 2 (CSI2 ®) Version 3.0. • Compliant with PHY Protocol Interface (PPI) to D-PHYTM Version 2.5. • Compliant with AMBA® APB Protocol Version 2.0. • Support PPI interface for D-PHY physical layer option. • Support Renesas original Vi

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MIPI DSI-2 Transmitter IP Core

• Compliant with Specification for Display Serial Interface 2 (DSI-2 SM) Version 1.1. • Compliant with PHY Protocol Interface (PPI) to D-PHYSM Version 2.1. • Compliant with AMBA® APB Protocol Version 2.0. • Support PPI interface for D-PHY physical layer option • Support De-facto standard

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MIPI D-PHY Transmitter/Receiver for Samsung 28nm FD-SOI

• Renesas MIPI D-PHY Transmitter/Receiver can be used for analog Transmitter/Receiver of following interface . - MIPI alliance Specification for D-PHY Version 2.1 15 December 2016. - MIPI alliance Specification for Display Serial Interface (DSI) Version 1.3.1 Aug 2015. - MIPI alliance Specific

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MIPI D-PHY Transmitter/Receiver for TSMC 40nm LP

• Renesas MIPI D-PHY Transmitter/Receiver can be used for analog Transmitter/Receiver of following interface . - MIPI alliance Specification for D-PHY Version 2.1 15 December 2016. - MIPI alliance Specification for Display Serial Interface (DSI) Version 1.3.1 Aug 2015. - MIPI alliance Specific

文件：107.37 Kbytes 页数：1 Pages

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32-bit RISC CPU IP

▪ 32-bit CPU + FPU, MMU option ▪ CPU with integrated vector FPU − 7MFLOPS / MHz ▪ Dual issue 32-bit CPU − 1.5DMIPS / MHz ▪ 5-stage pipeline

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32-bit RISC CPU IP

▪ 32-bit internal data bus ▪ General-purpose register architecture: 16 32-bit general general-purpose registers − Register bank for fast interrupt response (15 banks) ▪ RISC type instruction set: Instruction length: 16 bits / 32 bits mixed, 16-bit basic instruction for improving code effici

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SerDes PHY(PCIe3.0, USB3.1 SS) 10Gbps for TSMC 28nm HPC

▪ Renesas SerDes PHY can be used for analog transceiver of following interface. − PCI Express 3.0 / USB3.1 gen2 superspeed / Serial ATA 3.1/ 10GKR / SGMII *1 ▪ Multi-link support for area reduction in using multiple SerDes ▪ Technology is TSMC 28nm HPC+ 1p10M ▪ Supply voltage can be applied 0.

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SerDes PHY(PCIe2.1, USB3.0 SS) 5Gbps for TSMC 28nm HPC

Renesas SerDes PHY can be used for analog transceiver of following interface . − PCI Express 2.1 ( compliant with “PCI-Express Base Specification Revision 2.1”) *1 − USB3.0 SuperSpeed ( compliant with “Universal Serial Bus 3.0 Specification Revision 1.0 ) *1 ▪ PCI Express 2.1 and USB3.0 SuperSp

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USB2.0 PHY for TSMC 28nm HPC Multi-Port Transceiver

Renesas USB2.0 Transceiver can be used for analog transceiver of following interface . − Universal Serial Bus Specification Revision 2.0 *1 − Battery Charging Specification Revision 1.2 ▪ Supports Multi-port. ( 1 / 2 / 3 / 4 port type are available ) ▪ Technology is TSMC 28nm HPC+ 1p10M . ▪ S

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USB2.0 PHY for Samsung 28nm Multi-Port Transceiver

Renesas USB2.0 Transceiver can be used for analog transceiver of following interface . − Universal Serial Bus Specification Revision 2.0 − Battery Charging Specification Revision 1.2 ▪ Supports Multi port. ( 1 or 2 port type are available ) ▪ Technology is Samsung 28nm FD SOI 8M . ▪ Supply vo

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