SATURN USER NETWORK INTERFACE for J2/E3/T3

Description The PM7346 S/UNI-JET is an ATM physical layer processor with integrated DS3, E3, and J2 framers. It supports PLCP sublayer DS1, DS3, E1, and E3 processing and ATM cell delineation. Features The S/UNI®-JET is a single chip Asynchronous Transfer Mode (ATM) User Network Interface (UNI)

文件：1.86158 Mbytes 页数：341 Pages

PMC

SATURN USER NETWORK INTERFACE for J2/E3/T3

Description The PM7346 S/UNI-JET is an ATM physical layer processor with integrated DS3, E3, and J2 framers. It supports PLCP sublayer DS1, DS3, E1, and E3 processing and ATM cell delineation. Features The S/UNI®-JET is a single chip Asynchronous Transfer Mode (ATM) User Network Interface (UNI)

文件：1.86158 Mbytes 页数：341 Pages

PMC

622 Mbps ATM Traffic Management Device

Product Overview The PM73487 622 Mbps ATM Traffic Management Device (QRT) is an advanced communications device capable of supporting very large, high-performance ATM switching systems. The rich feature set of the QRT enables systems to offer many sophisticated network services. The QRT provides

文件：3.126 Mbytes 页数：251 Pages

PMC

622 Mbps ATM Traffic Management Device

Product Overview The PM73487 622 Mbps ATM Traffic Management Device (QRT) is an advanced communications device capable of supporting very large, high-performance ATM switching systems. The rich feature set of the QRT enables systems to offer many sophisticated network services. The QRT provides

文件：3.126 Mbytes 页数：251 Pages

PMC

5 Gbit/s ATM Switch Fabric Element

DESCRIPTION The PM73488 (QSE) is an advanced communications device that enables the implementation of high performance switching systems. The QSE is a 32 × 32 cell based switch element, with a total sustainable bandwidth of 5 Gb/s. (The peak, or raw, bandwidth is much more than that: about 8 Gb/s

文件：69.32 Kbytes 页数：4 Pages

PMC

Quad J2, E3 and DS-3 Framer

FEATURES • Quad DS-3, E3 (G.751 and G.832), and J2 framers. • Each channel can be independently configured to be a DS-3, E3, or J2 Framer. • Gapped transmit and receive clocks can be optionally generated for interface to devices which only need access to payload data bits. • Provides programma

文件：56.44 Kbytes 页数：2 Pages

PMC

Dual Serial Link, PHY Multiplexer

FEATURES • Integrated analog/digital device that interfaces a high-speed parallel bus to a high speed Low Voltage Differential Signal (LVDS) serial link with optional 1:1 protection. • For framers or modems without Utopia bus interfaces the S/UNI-DUPLEX provides cell delineation (I.432) across 1

文件：35.91 Kbytes 页数：2 Pages

PMC

Octal Serial Link Multiplexer

DESCRIPTION The PM7351 S/UNI-VORTEX is a monolithic integrated circuit typically used with its sister device, the S/UNI-DUPLEX, to implement a point-to-point serial backplane interconnect architecture. FEATURES • Integrated analog/digital device that interfaces a high speed parallel bus to 8 bi

文件：49.95 Kbytes 页数：4 Pages

PMC

Frame Engine and Datalink Manager

DESCRIPTION The PM7364 FREEDM-32 Frame Engine and Datalink Manager device is a monolithic integrated circuit that implements HDLC processing, and PCI Bus memory management functions for a maximum of 128 bi-directional channels. FEATURES • Single-chip Peripheral Component Interconnect (PCI) Bus

文件：39.74 Kbytes 页数：2 Pages

PMC

FRAME ENGINE AND DATA LINK MANAGER

DESCRIPTION The PM7366 FREEDM-8 Frame Engine and Datalink Manager device is a monolithic integrated circuit that implements HDLC processing, and PCI Bus memory management functions for a maximum of 128 bi-directional channels. FEATURES • Single-chip Peripheral Component Interconnect (PCI) Bus m

文件：2.2436 Mbytes 页数：286 Pages

PMC