QUAD 8 BIT CMOS D/A CONVERTERS WITH VOLTAGE OUTPUT

GENERAL DESCRIPTION The PM-7226 contains four 8-bit voltage output CMOS digital-to analog converters in a single chip. Also incorporated into this chip are four input latches and interface control logic. APPLICATIONS ● Auto Test Equipment ● Process and Industrial Control ● Scientific instrume

文件：1.00968 Mbytes 页数：20 Pages

AD

亚德诺

AAL1 Segmentation And Reassembly Processor

Description The AAL1 Segmentation And Reassembly (SAR) Processor (AAL1gator II™) provides DS1, E1, E3, or DS3 line interface access to an ATM Adaptation Layer One (AAL1) Constant Bit Rate (CBR) ATM network. It arbitrates access to an external SRAM for storage of the configuration, the user data,

文件：2.30048 Mbytes 页数：223 Pages

PMC

AAL1 Segmentation And Reassembly Processor

Description The AAL1 Segmentation And Reassembly (SAR) Processor (AAL1gator II™) provides DS1, E1, E3, or DS3 line interface access to an ATM Adaptation Layer One (AAL1) Constant Bit Rate (CBR) ATM network. It arbitrates access to an external SRAM for storage of the configuration, the user data,

文件：2.30048 Mbytes 页数：223 Pages

PMC

32 LINK CES/DBCES AAL1 SAR PROCESSOR

DESCRIPTION The AAL1 Segmentation And Reassembly (SAR) Processor (AAL1gator-32) is a monolithic single chip device that provides DS1, E1, E3, or DS3 line interface access to an ATM Adaptation Layer One (AAL1) Constant Bit Rate (CBR) ATM network. It arbitrates access to an external SRAM for storag

文件：4.41617 Mbytes 页数：489 Pages

PMC

32 LINK CES/DBCES AAL1 SAR PROCESSOR

DESCRIPTION The AAL1 Segmentation And Reassembly (SAR) Processor (AAL1gator-32) is a monolithic single chip device that provides DS1, E1, E3, or DS3 line interface access to an ATM Adaptation Layer One (AAL1) Constant Bit Rate (CBR) ATM network. It arbitrates access to an external SRAM for storag

文件：4.41617 Mbytes 页数：489 Pages

PMC

8 LINK CES/DBCES AAL1 SAR

DESCRIPTION The AAL1gator-8 AAL1 Segmentation And Reassembly (SAR) Processor is a monolithic single chip device that provides DS1, E1, E3, or DS3 line interface access to an ATM Adaptation Layer One (AAL1) Constant Bit Rate (CBR) ATM network. It arbitrates access to an external SRAM for storage o

文件：2.94476 Mbytes 页数：2 Pages

PMC

8 LINK CES/DBCES AAL1 SAR

DESCRIPTION The AAL1gator-8 AAL1 Segmentation And Reassembly (SAR) Processor is a monolithic single chip device that provides DS1, E1, E3, or DS3 line interface access to an ATM Adaptation Layer One (AAL1) Constant Bit Rate (CBR) ATM network. It arbitrates access to an external SRAM for storage o

文件：2.94476 Mbytes 页数：2 Pages

PMC

4 Link CES/DBCES AAL1 SAR

FEATURES • Supports four structured/unstructured T1 or E1 links, or one unstructured DS3, E3 or STS-1/STM-0 link over an AAL1 CBR ATM network. • Compliant with ATM Forums CES (AFVTOA-0078), and ITU-T I.363.1. • Supports up to 128 VCs. • Supports n x 64 (consecutive channels) an

文件：82.33 Kbytes 页数：2 Pages

PMC

ROUTING CONTROL, MONITORING, & POLICING 200 MBPS

DESCRIPTION The PM7322 Routing Control, Monitoring and Policing 200 Mbps (RCMP-200) device is a monolithic integrated circuit that implements ATM layer functions that include fault and performance monitoring, header translation and cell rate policing. The RCMP-200 is intended to be situated betwe

文件：695.91 Kbytes 页数：219 Pages

PMC

ROUTING CONTROL, MONITORING, & POLICING 200 MBPS

DESCRIPTION The PM7322 Routing Control, Monitoring and Policing 200 Mbps (RCMP-200) device is a monolithic integrated circuit that implements ATM layer functions that include fault and performance monitoring, header translation and cell rate policing. The RCMP-200 is intended to be situated betwe

文件：695.91 Kbytes 页数：219 Pages

PMC