PM7347-BI中文资料PMC数据手册PDF规格书

Description

The PM7346 S/UNI-JET is an ATM physical layer processor with integrated DS3, E3, and J2 framers. It supports PLCP sublayer DS1, DS3, E1, and E3 processing and ATM cell delineation.

Features

The S/UNI®-JET is a single chip Asynchronous Transfer Mode (ATM) User Network Interface (UNI) operating at 44.736 Mbit/s, 34.368 Mbit/s, and 6.312 Mbit/s that: • Conforms to AF-Physical (PHY)-0054.000, AF-PHY-0034.000 and AF-PHY-0029.000. • Implements ATM Direct Cell Mapping into DS1, DS3, E1, E3, and J2 transmission systems according to ITU-T Recommendation G.804.

• Provides a UTOPIA Level 2 compatible ATM-PHY Interface.

• Implements the Physical Layer Convergence Protocol (PLCP) for DS1 and DS3 transmission systems according to the ATM Forum User Network Interface Specification and ANSI TATSY-000773, TA-TSY-000772, and E1 and E3 transmission systems according to the ETSI 300-269 and ETSI 300-270.

• Supports Switched Multi-megabit Data Service (SMDS) and ATM mappings into various rate transmission systems as shown in Table 1:

• Implements the ATM physical layer for Broadband ISDN according to ITU-T Recommendation I.432.

• Provides on-chip DS3, E3 (G.751 and G.832), and J2 framers.

• Is configurable for sole DS3, E3, or J2 Framer use.

• Provides support for an arbitrary rate external transmission system interface up to a maximum rate of 52 Mbit/s, which enables the S/UNI-JET to be used as an ATM cell delineator.

• Uses the PMC-Sierra™ PM4351 COMET, PM4341 T1XC and PM6341 E1XC T1 and E1 framer/line interface chips for DS1 and E1 applications.

• Provides programmable pseudo-random test pattern generation, detection, and analysis features.

• Provides integral transmit and receive HDLC controller with 128-byte FIFO depth.

• Provides performance monitoring counters suitable for accumulation periods of up to 1 second.

• Provides an 8-bit microprocessor interface for configuration, control and status monitoring.

• Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board test purposes.

• Uses low power 3.3V CMOS technology with 5V tolerant inputs.

• Is available in a 256-pin SBGA package (27mm x 27mm).

Applications

• ATM or SMDS Switches, Multiplexers, and Routers

• SONET/SDH Mux E3/DS3 Tributary Interfaces

• PDH Mux J2/E3/DS3 Line Interfaces

• DS3/E3/J2 Digital Cross Connect Interfaces

• DS3/E3/J2 PPP Internet Access Interfaces

• DS3/E3/J2 Frame Relay Interfaces

• DSLAM Uplinks