PL138-48数据手册集成电路（IC）的时钟缓冲器驱动器规格书PDF

描述 Description

The PL138-48 family is a high performance low-cost 1:4 outputs Differential LVPECL fanout buffer.The family of Differential LVPECL buffers are designed to operate from a single power supply of 2.5V±5% or 3.3V±10%. The differential input pairs are designed to accept most standard input signal levels, using an appropriate resistor bias network, and produce a high quality set of outputs with the lowest possible skew on the outputs, which is guaranteed for part-to-part or lot-to lot skew.Designed to fit in a small form-factor package, PL138 family offers up to 1GHz of output operation with very low-power consumption, and lowest additive jitter of any comparable device. The Output Enable feature, when activated, allows the IC to consume less than 10µA of current.

特性 Features

• Four differential 2.5V/3.3V LVPECL output pairs
• Output Frequency: ≤1GHz
• Two selectable differential input pairs
• Translates any standard single-ended or differential input format to LVPECL output. It can accept the following standard input formats and more:
• LVPECL, LVCMOS, LVDS, HCSL, SSTL, LVHSTL, CML
• Output Skew: 25ps (typ.)
• Part-to-part skew: 140ps (typ.)
• Propagation delay: 1.5ns (typ.)
• Additive Jitter: <100fs (typ.)
• Operating Supply Voltage: 2.375V ~ 3.63V
• Operating temperature range from -40°C to 85°C
• Package availability: 20-pin TSSOP

简介

PL138-48属于集成电路（IC）的时钟缓冲器驱动器。由制造生产的PL138-48时钟缓冲器，驱动器时钟缓冲器和驱动器集成电路产品族中的产品用于帮助信号在系统中传输，常用作频率/时间参考信号，以同步系统内的活动。尽管这些器件最常用到的功能就是缓冲（即，为使信号不受驱动负载的影响而从某个信号源复制信号），但是该产品族中的某些器件还能执行其他功能，例如选择性改变缓冲信号路径、按某个整数值分割信号频率，或进行所用电信号格式转换。