PL133-67数据手册集成电路（IC）的时钟缓冲器驱动器规格书PDF

描述 Description

The PL133-67 is an advanced fanout buffer design for high performance, low-power, small form factor applications. The PL133-67 accepts a reference clock input from DC to 150MHz and provides 6 outputs of the same frequency.The PL133-67 is offered in a TSSOP-16L package and it offers the best phase noise, additive jitter performance, and lowest power consumption of any comparable IC.The PL133-67 outputs can be disabled to a high impedance (tri-state) by pulling low the OE pin. When the OE pin is high, the outputs are enabled and follow the REF input signal. When the OE pin is left open, a pull-up resistor on the chip will default the OE pin to logic 1 so the outputs are enabled.

特性 Features

• 1:6 LVCMOS output fanout buffer for DC to150MHz
• 8mA Output Drive Strength
• Low power consumption for portable applications
• Low input-output delay
• Output-Output skew less than 250ps
• Low Additive Phase Jitter of 60fs RMS
• 2.5V to 3.3V ±10% operation
• Operating temperature range from -40°C to 85°C
• Available in 16-Pin SOP GREEN/RoHS package

简介

PL133-67属于集成电路（IC）的时钟缓冲器驱动器。由制造生产的PL133-67时钟缓冲器，驱动器时钟缓冲器和驱动器集成电路产品族中的产品用于帮助信号在系统中传输，常用作频率/时间参考信号，以同步系统内的活动。尽管这些器件最常用到的功能就是缓冲（即，为使信号不受驱动负载的影响而从某个信号源复制信号），但是该产品族中的某些器件还能执行其他功能，例如选择性改变缓冲信号路径、按某个整数值分割信号频率，或进行所用电信号格式转换。