PL123-05中文资料Buffers数据手册Microchip规格书

描述 Description

The PL123-05/-09 (-05H/-09H for High Drive) are high performance, low skew, low jitter zero delay buffers designed to distribute high speed clocks. They have one (PL123-05) or two (PL123-09) low-skew output banks, of 4 outputs each, that are synchronized with the input. The PL123-09 allows control of the banks of outputs by using the S1 and S2 inputs as shown in the Selector Definition table on page 2 of the datasheet.The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than ±100ps, the device acts as a zero delay buffer. The input output propagation delay can be advanced or delayed by adjusting the load on the CLKOUT pin.These parts are not intended for 5V input-tolerant applications.

特性 Features

• Frequency Range 10MHz to 134MHz
• Output Options:
• 5 outputs PL123-05
• Zero input - output delay
• Optional Drive Strength:
• Standard (8mA) PL123-05/-09
• High (12mA) PL123-05H/-09H
• 3.3V ±10% operation
• Available in Commercial and Industrial temperature ranges
• Available in 8-Pin SOP packages

简介

PL123-05属于集成电路（IC）的时钟发生器PLL频率合成器。由制造生产的PL123-05时钟发生器，PLL，频率合成器时钟发生器、PLL 和频率合成器集成电路 (IC) 可为逻辑器件提供参考信号的稳定定时脉冲，这些器件包括计算机、微控制器、数据通信系统和图形/视频发生器。这些集成电路可能包括缓冲器、驱动器、分频器、倍频器、多路复用器、合成器、扇出分配器和预分频器。