PL123E-05中文资料Zero Delay Buffers Products数据手册Microchip规格书

描述 Description

The PL123E-05 (-05H for High Drive) is a high per-formance, low skew, low jitter zero delay buffer designed to distribute high speed clocks. It has five low-skew outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than ±100ps, the device acts as a zero delay buffer. The input output propagation delay can be advanced or delayed by adjusting the load on the CLKOUT pin.These parts are not intended for 5V input-tolerant applications.

特性 Features

• Frequency Range 10MHz to 220MHz
• Zero input - output delay
• Low output-to-output skew
• Optional Drive Strength:
• Standard (8mA) PL123E-05
• High (12mA) PL123E-05H
• 2.5V or 3.3V ±10% operation
• Available in 8-pin SOP packaging

简介

PL123E-05属于集成电路（IC）的时钟发生器PLL频率合成器。由制造生产的PL123E-05时钟发生器，PLL，频率合成器时钟发生器、PLL 和频率合成器集成电路 (IC) 可为逻辑器件提供参考信号的稳定定时脉冲，这些器件包括计算机、微控制器、数据通信系统和图形/视频发生器。这些集成电路可能包括缓冲器、驱动器、分频器、倍频器、多路复用器、合成器、扇出分配器和预分频器。