PL123中文资料Zero Delay Buffers Products数据手册Microchip规格书

描述 Description

The PL123-05/-09 (-05H/-09H for High Drive) are high performance, low skew, low jitter zero delay buffers designed to distribute high speed clocks. They have one (PL123-05) or two (PL123-09) low-skew output banks, of 4 outputs each, that are synchronized with the input. The PL123-09 allows control of the banks of outputs by using the S1 and S2 inputs as shown in the Selector Definition table on page 2 of the datasheet.The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than ±100ps, the device acts as a zero delay buffer. The input output propagation delay can be advanced or delayed by adjusting the load on the CLKOUT pin.These parts are not intended for 5V input-tolerant applications.

特性 Features

·Frequency Range 10MHz to 134MHz
·Output Options:·5 outputs PL123-05

·Zero input - output delay
·Optional Drive Strength:·Standard (8mA) PL123-05/-09
·High (12mA) PL123-05H/-09H

·3.3V ±10% operation
·Available in Commercial and Industrial temperature ranges
·Available in 8-Pin SOP packages

简介

PL123属于集成电路（IC）的时钟缓冲器驱动器。由制造生产的PL123时钟缓冲器，驱动器时钟缓冲器和驱动器集成电路产品族中的产品用于帮助信号在系统中传输，常用作频率/时间参考信号，以同步系统内的活动。尽管这些器件最常用到的功能就是缓冲（即，为使信号不受驱动负载的影响而从某个信号源复制信号），但是该产品族中的某些器件还能执行其他功能，例如选择性改变缓冲信号路径、按某个整数值分割信号频率，或进行所用电信号格式转换。