NB4L339中文资料NB4L339: 2.5 V / 3.3 V Clock Distribution IC for SONET/SDH数据手册ONSEMI规格书

描述 Description

The NB4L339 is a multi-function Clock generator featuring a 2:1 Clock multiplexer front end and simultaneously outputs a selection of four different divide ratios from its four divider blocks; div1, div2, div4 and div8. One divide block has a choice of div1 or div2. The output of each divider block is fanned-out to two identical differential LVPECL copies of the selected clock. All outputs provide standard LVPECL voltage levels when externally terminated with a 50-ohm resistor to VCC - 2 V. The differential Clock inputs incorporate internal 50-ohm termination resistors and will accept LVPECL, CML or LVDS logic levels. The common Output Enable pin (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock. Therefore, all associated specification limits are referenced to the negative edge of the clock input. This device is housed in a 5x5 mm 32 pin QFN package.

特性 Features

0.5 ps Typical RMS Random Clock Period Jitter
Very Low Jitter Clock Output
LVPECL, CML or LVDS Input Compatible
Multi Level Input Interface
0.15 ps Typical RMS Phase Jitter
Low Skew LVPECL Outputs, 15 ps typical

应用 Application

Clock Generation for SONET applications

简介

NB4L339属于开发板套件编程器的评估演示板及套件。由制造生产的NB4L339评估和演示板及套件该系列产品提供了一种方便的方法，在经过验证的实施环境中评估某些重点器件的性能或特性。评估方法通常有完善的文档说明，并且视乎具体情况由评估软件提供支持。产品通常由印刷电路板组成，板上已装有重点器件以及必要或有用的支持元器件，另外也可能包括其他组件，例如电缆或电源。对于数量特别多或类别独特的器件类别(如 ADC、DAC 和开关模式电源)，评估平台可组合为一个单独的产品系列。