NB3V8312C数据手册集成电路（IC）的时钟缓冲器驱动器规格书PDF

描述 Description

The NB3V8312C is a high performance, low skew LVCMOS fanout buffer which can distribute 12 ultra-low jitter clocks from an LVCMOS/LVTTL input up to 250 MHz. The 12 LVCMOS output pins drive 50Ωseries or parallel terminated transmission lines. The outputs can also be disabled to a high impedance (tri-stated) via the OE input, or enabled when High. The NB3V8312C provides an enable input, CLK_EN pin, which synchronously enables or disables the clock outputs while in the LOW state. Since this input is internally synchronized to the input clock, changing only when the input is LOW, potential output glitching or runt pulse generation is eliminated. Separate VDD core and VDDO output supplies allow the output buffers to operate at the same supply as the VDD (VDD = VDDO) or from a lower supply voltage. Compared to single-supply operation, dual supply operation enables lower power consumption and output-level compatibility. The VDD core supply voltage can be set to 3.3 V, 2.5 V or 1.8 V, while the VDDO output supply voltage can be set to 3.3 V, 2.5 V, or 1.8 V, with the constraint that VDD >/= VDDO.

特性 Features

• VDD core supply voltage can be set to 3.3 V, 2.5 V or 1.8 V
• VDDO output supply voltage can be set to 3.3 V, 2.5 V, or 1.8 V, with the constraint that VDD >/= VDDO
• 250 MHz Maximum Clock Frequency
• Accepts LVCMOS, LVTTL Clock Inputs
• 12 LVCMOS Clock Outputs
• 150 ps Max. Skew Between Outputs
• Temp. Range 40C to +85C
• 32pin LQFP and QFN Packages
• Synchronous Clock Enable

应用 Application

• Networking
• Telecom
• Storage Area Networks
• Servers
• Routers
• Switches

简介

NB3V8312C属于集成电路（IC）的时钟缓冲器驱动器。由制造生产的NB3V8312C时钟缓冲器，驱动器时钟缓冲器和驱动器集成电路产品族中的产品用于帮助信号在系统中传输，常用作频率/时间参考信号，以同步系统内的活动。尽管这些器件最常用到的功能就是缓冲（即，为使信号不受驱动负载的影响而从某个信号源复制信号），但是该产品族中的某些器件还能执行其他功能，例如选择性改变缓冲信号路径、按某个整数值分割信号频率，或进行所用电信号格式转换。