NB3RL02中文资料Clock Fanout Buffer, 2-Channel, Low Phase Noise数据手册ONSEMI规格书

描述 Description

The NB3RL02 is a low-skew, low jitter 1:2 clock fan-out buffer, ideal for use in portable end-equipment, such as mobile phones. With integrated LDO and output control circuitry. The MCLK_IN pin has an AC coupling capacitor and will directly accept a square or sine wave clock input, such as a temperature compensated crystal oscillator (TCXO). The minimum acceptable input amplitude of the sine wave is 300 mV peak-to-peak. The two clock outputs are enabled by control inputs CLK_REQ1 and CLK_REQ2. The NB3RL02 has an integrated Low-Drop-Out (LDO) voltage regulator which accepts input voltages from 2.3 V to 5.5 V and outputs 1.8 V at Iout = 50 mA. This 1.8 V supply is externally available to provide regulated power to peripheral devices, such as a TCXO. The adaptive clock output buffers offer controlled slew-rate over a wide capacitive loading range which minimizes EMI emissions, maintains signal integrity, and minimizes ringing caused by signal reflections on the clock distribution lines. The NB3RL02 is offered in a 0.4 mm pitch wafer-level-chip-scale (WLCS) package (0.77 mm x 1.57 mm) and is optimized for very low standby current consumption.

特性 Features

• Low Additive Noise: -149 dBc/Hz at 10 kHz Offset Phase Noise
• Regulated 1.8 V Output Supply Available for External Clock Source,ie. TCX0
• Ultra-Small Package: 8-ball: 0.4 mm Pitch WLCS (0.77 mm x 1.57 mm)
• ESD Performance Exceeds JESD 22: 2000 V Human Body Model

应用 Application

• Wireless LAN
• FM Radio
• WiMAX
• Wireless BT
• Cellular Phones
• Global Positioning Systems (GPS)

简介

NB3RL02属于集成电路（IC）的时钟缓冲器驱动器。由制造生产的NB3RL02时钟缓冲器，驱动器时钟缓冲器和驱动器集成电路产品族中的产品用于帮助信号在系统中传输，常用作频率/时间参考信号，以同步系统内的活动。尽管这些器件最常用到的功能就是缓冲（即，为使信号不受驱动负载的影响而从某个信号源复制信号），但是该产品族中的某些器件还能执行其他功能，例如选择性改变缓冲信号路径、按某个整数值分割信号频率，或进行所用电信号格式转换。